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authorRon Dreslinski <rdreslin@umich.edu>2006-11-12 09:06:15 -0500
committerRon Dreslinski <rdreslin@umich.edu>2006-11-12 09:06:15 -0500
commita200bccc2065d776d0face971610588f438998e7 (patch)
tree5a6f1e1fe5f8cca4da7bbc51ed492bc996585fa3 /src/mem
parent29cefcbf1353b90f6b12334f8554efa87bd659c8 (diff)
downloadgem5-a200bccc2065d776d0face971610588f438998e7.tar.xz
Handle packets being deleted by lower level properly.
Fixes for Mem Leak associated with Writebacks. src/mem/cache/miss/mshr_queue.cc: Fixes for Mem Leak associated with Writebacks. (Double Delete removed) --HG-- extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/cache_impl.hh25
-rw-r--r--src/mem/cache/miss/mshr_queue.cc5
2 files changed, 17 insertions, 13 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 8acc67b69..df59b0a4f 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -53,6 +53,8 @@
#include "sim/sim_exit.hh" // for SimExitEvent
+bool SIGNAL_NACK_HACK;
+
template<class TagStore, class Buffering, class Coherence>
bool
Cache<TagStore,Buffering,Coherence>::
@@ -242,6 +244,11 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
missQueue->handleMiss(pkt, size, curTick + hitLatency);
}
+ if (pkt->cmd == Packet::Writeback) {
+ //Need to clean up the packet on a writeback miss, but leave the request
+ delete pkt;
+ }
+
return true;
}
@@ -265,6 +272,7 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
assert(!doMasterRequest() || missQueue->havePending());
assert(!pkt || pkt->time <= curTick);
+ SIGNAL_NACK_HACK = false;
return pkt;
}
@@ -273,16 +281,15 @@ void
Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
bool success)
{
- if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
- if (!mshr->pkt->needsResponse()
- && !(mshr->pkt->cmd == Packet::UpgradeReq)
- && (pkt && (pkt->flags & SATISFIED))) {
- //Writeback, clean up the non copy version of the packet
- delete pkt;
- }
+ if (success && !(SIGNAL_NACK_HACK)) {
+ //Remember if it was an upgrade because writeback MSHR's are removed
+ //in Mark in Service
+ bool upgrade = (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq);
+
missQueue->markInService(mshr->pkt, mshr);
+
//Temp Hack for UPGRADES
- if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
+ if (upgrade) {
assert(pkt); //Upgrades need to be fixed
pkt->flags &= ~CACHE_LINE_FILL;
BlkType *blk = tags->findBlock(pkt);
@@ -300,6 +307,7 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
}
} else if (pkt && !pkt->req->isUncacheable()) {
pkt->flags &= ~NACKED_LINE;
+ SIGNAL_NACK_HACK = false;
pkt->flags &= ~SATISFIED;
pkt->flags &= ~SNOOP_COMMIT;
@@ -404,6 +412,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
assert(!(pkt->flags & SATISFIED));
pkt->flags |= SATISFIED;
pkt->flags |= NACKED_LINE;
+ SIGNAL_NACK_HACK = true;
///@todo NACK's from other levels
//warn("NACKs from devices not connected to the same bus "
//"not implemented\n");
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index d3a7a7933..6cb62429d 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -198,11 +198,6 @@ MSHRQueue::markInService(MSHR* mshr)
//assert(mshr == pendingList.front());
if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)) {
assert(mshr->getNumTargets() == 0);
- if ((mshr->pkt->flags & SATISFIED) && (mshr->pkt->cmd == Packet::Writeback)) {
- //Writeback hit, so delete it
- //otherwise the consumer will delete it
- delete mshr->pkt->req;
- }
deallocate(mshr);
return;
}