Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

15 files changed, 105 insertions, 440 deletions

diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
index 269cf4403..e2e858494 100644
--- a/src/mem/MemObject.py
+++ b/src/mem/MemObject.py
@@ -27,7 +27,6 @@
 # Authors: Ron Dreslinski
 
 from m5.SimObject import SimObject
-from m5.SimObject import SimObject
 
 class MemObject(SimObject):
     type = 'MemObject'
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index d6adb05d1..6cfa5a2ac 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -39,7 +39,7 @@
 
 #include "base/trace.hh"
 #include "mem/bridge.hh"
-#include "sim/builder.hh"
+#include "params/Bridge.hh"
 
 Bridge::BridgePort::BridgePort(const std::string &_name,
                                Bridge *_bridge, BridgePort *_otherPort,
@@ -359,50 +359,8 @@ Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp,
     snoop = false;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge)
-
-   Param<int> req_size_a;
-   Param<int> req_size_b;
-   Param<int> resp_size_a;
-   Param<int> resp_size_b;
-   Param<Tick> delay;
-   Param<Tick> nack_delay;
-   Param<bool> write_ack;
-   Param<bool> fix_partial_write_a;
-   Param<bool> fix_partial_write_b;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bridge)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge)
-
-    INIT_PARAM(req_size_a, "The size of the queue for requests coming into side a"),
-    INIT_PARAM(req_size_b, "The size of the queue for requests coming into side b"),
-    INIT_PARAM(resp_size_a, "The size of the queue for responses coming into side a"),
-    INIT_PARAM(resp_size_b, "The size of the queue for responses coming into side b"),
-    INIT_PARAM(delay, "The miminum delay to cross this bridge"),
-    INIT_PARAM(nack_delay, "The minimum delay to nack a packet"),
-    INIT_PARAM(write_ack, "Acknowledge any writes that are received."),
-    INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"),
-    INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received")
-
-END_INIT_SIM_OBJECT_PARAMS(Bridge)
-
-CREATE_SIM_OBJECT(Bridge)
+Bridge *
+BridgeParams::create()
 {
-    Bridge::Params *p = new Bridge::Params;
-    p->name = getInstanceName();
-    p->req_size_a = req_size_a;
-    p->req_size_b = req_size_b;
-    p->resp_size_a = resp_size_a;
-    p->resp_size_b = resp_size_b;
-    p->delay = delay;
-    p->nack_delay = nack_delay;
-    p->write_ack = write_ack;
-    p->fix_partial_write_a = fix_partial_write_a;
-    p->fix_partial_write_b = fix_partial_write_b;
-    return new Bridge(p);
+    return new Bridge(this);
 }
-
-REGISTER_SIM_OBJECT("Bridge", Bridge)
-
-
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index acae2f126..d3bbf2ddf 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -45,6 +45,7 @@
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
+#include "params/Bridge.hh"
 #include "sim/eventq.hh"
 
 class Bridge : public MemObject
@@ -191,19 +192,7 @@ class Bridge : public MemObject
     bool ackWrites;
 
   public:
-    struct Params
-    {
-        std::string name;
-        int req_size_a;
-        int req_size_b;
-        int resp_size_a;
-        int resp_size_b;
-        Tick delay;
-        Tick nack_delay;
-        bool write_ack;
-        bool fix_partial_write_a;
-        bool fix_partial_write_b;
-    };
+    typedef BridgeParams Params;
 
   protected:
     Params *_params;
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 1fad13c5a..518c9dbfa 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -39,7 +39,7 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "mem/bus.hh"
-#include "sim/builder.hh"
+#include "params/Bus.hh"
 
 Port *
 Bus::getPort(const std::string &if_name, int idx)
@@ -599,28 +599,8 @@ Bus::startup()
         tickNextIdle = (curTick / clock) * clock + clock;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
-
-    Param<int> bus_id;
-    Param<int> clock;
-    Param<int> width;
-    Param<bool> responder_set;
-    Param<int> block_size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bus)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
-    INIT_PARAM(bus_id, "a globally unique bus id"),
-    INIT_PARAM(clock, "bus clock speed"),
-    INIT_PARAM(width, "width of the bus (bits)"),
-    INIT_PARAM(responder_set, "Is a default responder set by the user"),
-    INIT_PARAM(block_size, "Default blocksize if no device has one")
-END_INIT_SIM_OBJECT_PARAMS(Bus)
-
-CREATE_SIM_OBJECT(Bus)
+Bus *
+BusParams::create()
 {
-    return new Bus(getInstanceName(), bus_id, clock, width, responder_set,
-            block_size);
+    return new Bus(name, bus_id, clock, width, responder_set, block_size);
 }
-
-REGISTER_SIM_OBJECT("Bus", Bus)
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 65418b68d..4c9592a1b 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -36,13 +36,13 @@
 #include <vector>
 
 // Must be included first to determine which caches we want
+#include "enums/Prefetch.hh"
 #include "mem/config/cache.hh"
 #include "mem/config/prefetch.hh"
-
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/cache.hh"
 #include "mem/bus.hh"
-#include "sim/builder.hh"
+#include "params/BaseCache.hh"
 
 // Tag Templates
 #if defined(USE_CACHE_LRU)
@@ -80,100 +80,16 @@
 using namespace std;
 using namespace TheISA;
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-    Param<int> size;
-    Param<int> assoc;
-    Param<int> block_size;
-    Param<int> latency;
-    Param<int> mshrs;
-    Param<int> tgts_per_mshr;
-    Param<int> write_buffers;
-    Param<bool> prioritizeRequests;
-    Param<Addr> trace_addr;
-    Param<int> hash_delay;
-#if defined(USE_CACHE_IIC)
-    SimObjectParam<Repl *> repl;
-#endif
-    Param<int> subblock_size;
-    Param<Counter> max_miss_count;
-    VectorParam<Range<Addr> > addr_range;
-//    SimObjectParam<MemTraceWriter *> mem_trace;
-    Param<bool> split;
-    Param<int> split_size;
-    Param<bool> lifo;
-    Param<bool> two_queue;
-    Param<bool> prefetch_miss;
-    Param<bool> prefetch_access;
-    Param<int> prefetcher_size;
-    Param<bool> prefetch_past_page;
-    Param<bool> prefetch_serial_squash;
-    Param<Tick> prefetch_latency;
-    Param<int> prefetch_degree;
-    Param<string> prefetch_policy;
-    Param<bool> prefetch_cache_check_push;
-    Param<bool> prefetch_use_cpu_id;
-    Param<bool> prefetch_data_accesses_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-    INIT_PARAM(size, "capacity in bytes"),
-    INIT_PARAM(assoc, "associativity"),
-    INIT_PARAM(block_size, "block size in bytes"),
-    INIT_PARAM(latency, "hit latency in CPU cycles"),
-    INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
-    INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
-    INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
-    INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
-                    false),
-    INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
-
-    INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
-#if defined(USE_CACHE_IIC)
-    INIT_PARAM_DFLT(repl, "replacement policy",NULL),
-#endif
-    INIT_PARAM_DFLT(subblock_size,
-                    "Size of subblock in IIC used for compression",
-                    0),
-    INIT_PARAM_DFLT(max_miss_count,
-                    "The number of misses to handle before calling exit",
-                    0),
-    INIT_PARAM_DFLT(addr_range, "The address range in bytes",
-                    vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
-//    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
-    INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
-    INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
-    INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
-    INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
-    INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
-    INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
-    INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
-    INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
-    INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
-    INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
-    INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
-    INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
-    INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
-    INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
-    INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
-END_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-
 #define BUILD_CACHE(TAGS, tags)                                      \
     do {                                                                \
-        BasePrefetcher *pf;                                           \
-        if (pf_policy == "tagged") {                                    \
+        BasePrefetcher *pf;                                             \
+        if (prefetch_policy == Enums::tagged) {                         \
             BUILD_TAGGED_PREFETCHER(TAGS);                              \
         }                                                               \
-        else if (pf_policy == "stride") {                               \
+        else if (prefetch_policy == Enums::stride) {                    \
             BUILD_STRIDED_PREFETCHER(TAGS);                             \
         }                                                               \
-        else if (pf_policy == "ghb") {                                  \
+        else if (prefetch_policy == Enums::ghb) {                       \
             BUILD_GHB_PREFETCHER(TAGS);                                 \
         }                                                               \
         else {                                                          \
@@ -184,7 +100,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
                                    true,                                \
                                    prefetch_miss);                      \
         Cache<TAGS> *retval =                                        \
-            new Cache<TAGS>(getInstanceName(), params);              \
+            new Cache<TAGS>(name, params);                              \
         return retval;                                                  \
     } while (0)
 
@@ -314,11 +230,10 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 #endif
 
-CREATE_SIM_OBJECT(BaseCache)
+BaseCache *
+BaseCacheParams::create()
 {
-    string name = getInstanceName();
     int numSets = size / (assoc * block_size);
-    string pf_policy = prefetch_policy;
     if (subblock_size == 0) {
         subblock_size = block_size;
     }
@@ -329,24 +244,21 @@ CREATE_SIM_OBJECT(BaseCache)
                                   max_miss_count);
 
     //Warnings about prefetcher policy
-    if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
-        panic("With no prefetcher, you shouldn't prefetch from"
-              " either miss or access stream\n");
+    if (prefetch_policy == Enums::none) {
+        if (prefetch_miss || prefetch_access)
+            panic("With no prefetcher, you shouldn't prefetch from"
+                  " either miss or access stream\n");
     }
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
-         pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
-        warn("With this prefetcher you should chose a prefetch"
-             " stream (miss or access)\nNo Prefetching will occur\n");
-    }
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
-         pf_policy == "ghb") && prefetch_miss && prefetch_access) {
-        panic("Can't do prefetches from both miss and access"
-              " stream\n");
-    }
-    if (pf_policy != "tagged" && pf_policy != "stride" &&
-        pf_policy != "ghb"    && pf_policy != "none") {
-        panic("Unrecognized form of a prefetcher: %s, try using"
-              "['none','stride','tagged','ghb']\n", pf_policy);
+
+    if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
+        prefetch_policy == Enums::ghb) {
+
+        if (!prefetch_miss && !prefetch_access)
+            warn("With this prefetcher you should chose a prefetch"
+                 " stream (miss or access)\nNo Prefetching will occur\n");
+
+        if (prefetch_miss && prefetch_access)
+            panic("Can't do prefetches from both miss and access stream");
     }
 
 #if defined(USE_CACHE_IIC)
@@ -367,8 +279,3 @@ CREATE_SIM_OBJECT(BaseCache)
     BUILD_CACHES;
     return NULL;
 }
-
-REGISTER_SIM_OBJECT("BaseCache", BaseCache)
-
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 3fcaec4fa..a65c44f22 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -40,4 +40,3 @@ Source('split_lru.cc')
 
 SimObject('Repl.py')
 Source('repl/gen.cc')
-Source('repl/repl.cc')
diff --git a/src/mem/cache/tags/repl/gen.cc b/src/mem/cache/tags/repl/gen.cc
index ec1c2aaf3..7d1566300 100644
--- a/src/mem/cache/tags/repl/gen.cc
+++ b/src/mem/cache/tags/repl/gen.cc
@@ -39,7 +39,7 @@
 #include "base/misc.hh"
 #include "mem/cache/tags/iic.hh"
 #include "mem/cache/tags/repl/gen.hh"
-#include "sim/builder.hh"
+#include "params/GenRepl.hh"
 #include "sim/host.hh"
 
 using namespace std;
@@ -247,31 +247,8 @@ GenRepl::findTagPtr(unsigned long index)
     return false;
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-    Param<int> num_pools;
-    Param<int> fresh_res;
-    Param<int> pool_res;
-
-END_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-    INIT_PARAM(num_pools, "capacity in bytes"),
-    INIT_PARAM(fresh_res, "associativity"),
-    INIT_PARAM(pool_res, "block size in bytes")
-
-END_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-
-CREATE_SIM_OBJECT(GenRepl)
+GenRepl *
+GenReplParams::create()
 {
-    return new GenRepl(getInstanceName(), num_pools, fresh_res, pool_res);
+    return new GenRepl(name, num_pools, fresh_res, pool_res);
 }
-
-REGISTER_SIM_OBJECT("GenRepl", GenRepl)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/tags/repl/repl.cc b/src/mem/cache/tags/repl/repl.cc
deleted file mode 100644
index ce781eb9f..000000000
--- a/src/mem/cache/tags/repl/repl.cc
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- *          Nathan Binkert
- */
-
-/**
- * Definitions of the base replacement class.
- */
-
-#include "sim/param.hh"
-#include "mem/cache/tags/repl/repl.hh"
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Repl", Repl)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/dram.cc b/src/mem/dram.cc
index 394c70db6..75146f9ed 100644
--- a/src/mem/dram.cc
+++ b/src/mem/dram.cc
@@ -99,11 +99,10 @@ Kluwer Academic, pages 291-310, March, 2000.
  * Definition of a DRAM like main memory.
  */
 
+#include <cstdlib>
+#include <string>
 
 #include "mem/dram.hh"
-#include "sim/builder.hh"
-#include <stdlib.h>
-#include <string>
 
 extern int maxThreadsPerCPU;
 
@@ -174,7 +173,7 @@ extern int maxThreadsPerCPU;
 
 
 
-DRAMMemory::DRAMMemory(Params *p)
+DRAMMemory::DRAMMemory(const Params *p)
     : PhysicalMemory(p), cpu_ratio(p->cpu_ratio), bus_width(p->bus_width),
       mem_type(p->mem_type), mem_actpolicy(p->mem_actpolicy),
       memctrladdr_type(p->memctrladdr_type), act_lat(p->act_lat),
@@ -197,7 +196,7 @@ DRAMMemory::DRAMMemory(Params *p)
       memctrlpipe_enable(false), time_last_access(0)
 {
     warn("This DRAM module has not been tested with the new memory system at all!");
-        bank_size = (params()->addrRange.size() + 1) / num_banks;
+        bank_size = (p->range.size() + 1) / num_banks;
         num_rows = bank_size / SD_ROW_SIZE; /* 0x1000 size of row 4Kbtye */
         active_row = new int[num_banks];
         last_bank = num_banks+1;
@@ -2666,81 +2665,8 @@ else
 return precharge;
 }
 
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-    Param<std::string> file;
-    Param<Range<Addr> > range;
-    Param<Tick> latency;
-    /* additional params for dram protocol*/
-    Param<int> cpu_ratio;
-    Param<std::string> mem_type;
-    Param<std::string> mem_actpolicy;
-    Param<std::string> memctrladdr_type;
-    Param<int> bus_width;
-    Param<int> act_lat;
-    Param<int> cas_lat;
-    Param<int> war_lat;
-    Param<int> pre_lat;
-    Param<int> dpl_lat;
-    Param<int> trc_lat;
-    Param<int> num_banks;
-    Param<int> num_cpus;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-    INIT_PARAM_DFLT(file, "memory mapped file", ""),
-    INIT_PARAM(range, "Device Address Range"),
-    INIT_PARAM(latency, "Memory access latency"),
-
-    /* additional params for dram protocol*/
-    INIT_PARAM_DFLT(cpu_ratio,"ratio between CPU speed and memory bus speed",5),
-    INIT_PARAM_DFLT(mem_type,"type of DRAM","SDRAM"),
-    INIT_PARAM_DFLT(mem_actpolicy,"open / closed page policy","open"),
-    INIT_PARAM_DFLT(memctrladdr_type,"interleaved or direct mapping","interleaved"),
-    INIT_PARAM_DFLT(bus_width,"memory access bus width",16),
-    INIT_PARAM_DFLT(act_lat,"RAS to CAS delay",2),
-    INIT_PARAM_DFLT(cas_lat,"CAS delay",1),
-    INIT_PARAM_DFLT(war_lat,"write after read delay",2),
-    INIT_PARAM_DFLT(pre_lat,"precharge delay",2),
-    INIT_PARAM_DFLT(dpl_lat,"data in to precharge delay",2),
-    INIT_PARAM_DFLT(trc_lat,"row cycle delay",6),
-    INIT_PARAM_DFLT(num_banks,"Number of Banks",4),
-    INIT_PARAM_DFLT(num_cpus,"Number of CPUs connected to DRAM",4)
-
-END_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-CREATE_SIM_OBJECT(DRAMMemory)
+DRAMMemory *
+DRAMMemoryParams::create()
 {
-    DRAMMemory::Params *p = new DRAMMemory::Params;
-    p->name = getInstanceName();
-    p->addrRange = range;
-    p->latency = latency;
-
-    /* additional params for dram */
-    p->cpu_ratio = cpu_ratio;
-    p->bus_width = bus_width;
-    p->mem_type = mem_type;
-    p->mem_actpolicy = mem_actpolicy;
-    p->memctrladdr_type = memctrladdr_type;
-    p->act_lat = act_lat;
-    p->cas_lat = cas_lat;
-    p->war_lat = war_lat;
-    p->pre_lat = pre_lat;
-    p->dpl_lat = dpl_lat;
-    p->trc_lat = trc_lat;
-    p->num_banks = num_banks;
-    p->num_cpus = num_cpus;
-
-    return new DRAMMemory(p);
+    return new DRAMMemory(this);
 }
-
-REGISTER_SIM_OBJECT("DRAMMemory", DRAMMemory)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
-
-
diff --git a/src/mem/dram.hh b/src/mem/dram.hh
index 9d2f60ee8..352ca96ae 100644
--- a/src/mem/dram.hh
+++ b/src/mem/dram.hh
@@ -38,6 +38,7 @@
 
 #include "base/statistics.hh"
 #include "mem/physical.hh"
+#include "params/DRAMMemory.hh"
 
 class DRAMMemory : public PhysicalMemory
 {
@@ -144,28 +145,16 @@ class DRAMMemory : public PhysicalMemory
     int prechargeBanksAround(int bank);
 
   public:
-    struct Params : public PhysicalMemory::Params
+    typedef DRAMMemoryParams Params;
+    DRAMMemory(const Params *p);
+
+    const Params *
+    params() const
     {
-        /* additional params for dram protocol*/
-        int cpu_ratio;
-        int bus_width;
-
-        std::string mem_type; /* DRDRAM, SDRAM */
-        std::string mem_actpolicy; /* closed, open */
-        std::string memctrladdr_type; /* interleaved, anythingelse */
-
-        int act_lat;
-        int cas_lat;
-        int war_lat;
-        int pre_lat;
-        int dpl_lat;
-        int trc_lat;
-        int num_banks;
-        int num_cpus;
-
-    };
+        return dynamic_cast<const Params *>(_params);
+    }
+
     virtual void regStats();
-    DRAMMemory(Params *p);
 };
 
 #endif// __MEM_DRAM_HH__
diff --git a/src/mem/mem_object.cc b/src/mem/mem_object.cc
index ef31cf999..b40709eb2 100644
--- a/src/mem/mem_object.cc
+++ b/src/mem/mem_object.cc
@@ -29,16 +29,19 @@
  */
 
 #include "mem/mem_object.hh"
-#include "sim/param.hh"
+
+MemObject::MemObject(const Params *params)
+    : SimObject(params)
+{
+}
 
 MemObject::MemObject(const std::string &name)
     : SimObject(name)
 {
 }
+
 void
 MemObject::deletePortRefs(Port *p)
 {
     panic("This object does not support port deletion\n");
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)
diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh
index ec6fa2b2a..79e555cda 100644
--- a/src/mem/mem_object.hh
+++ b/src/mem/mem_object.hh
@@ -36,8 +36,9 @@
 #ifndef __MEM_MEM_OBJECT_HH__
 #define __MEM_MEM_OBJECT_HH__
 
-#include "sim/sim_object.hh"
 #include "mem/port.hh"
+#include "params/MemObject.hh"
+#include "sim/sim_object.hh"
 
 /**
  * The base MemoryObject class, allows for an accesor function to a
@@ -46,8 +47,16 @@
 class MemObject : public SimObject
 {
   public:
+    typedef MemObjectParams Params;
+    MemObject(const Params *params);
     MemObject(const std::string &name);
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
   public:
     /** Additional function to return the Port of a memory object. */
     virtual Port *getPort(const std::string &if_name, int idx = -1) = 0;
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index b29a07078..a00d743cd 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -43,7 +43,6 @@
 #include "base/intmath.hh"
 #include "base/trace.hh"
 #include "mem/page_table.hh"
-#include "sim/builder.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 2742eca51..b96fb8a56 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -44,23 +44,21 @@
 #include "config/full_system.hh"
 #include "mem/packet_access.hh"
 #include "mem/physical.hh"
-#include "sim/builder.hh"
 #include "sim/eventq.hh"
 #include "sim/host.hh"
 
 using namespace std;
 using namespace TheISA;
 
-PhysicalMemory::PhysicalMemory(Params *p)
-    : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p)
+PhysicalMemory::PhysicalMemory(const Params *p)
+    : MemObject(p), pmemAddr(NULL), lat(p->latency)
 {
-    if (params()->addrRange.size() % TheISA::PageBytes != 0)
+    if (params()->range.size() % TheISA::PageBytes != 0)
         panic("Memory Size not divisible by page size\n");
 
     int map_flags = MAP_ANON | MAP_PRIVATE;
-    pmemAddr =
-        (uint8_t *)mmap(NULL, params()->addrRange.size(),
-                        PROT_READ | PROT_WRITE, map_flags, -1, 0);
+    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
+                               PROT_READ | PROT_WRITE, map_flags, -1, 0);
 
     if (pmemAddr == (void *)MAP_FAILED) {
         perror("mmap");
@@ -68,8 +66,8 @@ PhysicalMemory::PhysicalMemory(Params *p)
     }
 
     //If requested, initialize all the memory to 0
-    if(params()->zero)
-        memset(pmemAddr, 0, params()->addrRange.size());
+    if (p->zero)
+        memset(pmemAddr, 0, p->range.size());
 
     pagePtr = 0;
 }
@@ -90,7 +88,7 @@ PhysicalMemory::init()
 PhysicalMemory::~PhysicalMemory()
 {
     if (pmemAddr)
-        munmap((char*)pmemAddr, params()->addrRange.size());
+        munmap((char*)pmemAddr, params()->range.size());
     //Remove memPorts?
 }
 
@@ -384,7 +382,7 @@ PhysicalMemory::getAddressRanges(AddrRangeList &resp, bool &snoop)
 {
     snoop = false;
     resp.clear();
-    resp.push_back(RangeSize(start(), params()->addrRange.size()));
+    resp.push_back(RangeSize(start(), params()->range.size()));
 }
 
 int
@@ -446,7 +444,8 @@ PhysicalMemory::serialize(ostream &os)
         fatal("Insufficient memory to allocate compression state for %s\n",
                 filename);
 
-    if (gzwrite(compressedMem, pmemAddr, params()->addrRange.size()) != params()->addrRange.size()) {
+    if (gzwrite(compressedMem, pmemAddr, params()->range.size()) !=
+        params()->range.size()) {
         fatal("Write failed on physical memory checkpoint file '%s'\n",
               filename);
     }
@@ -488,10 +487,10 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
     // unmap file that was mmaped in the constructor
     // This is done here to make sure that gzip and open don't muck with our
     // nice large space of memory before we reallocate it
-    munmap((char*)pmemAddr, params()->addrRange.size());
+    munmap((char*)pmemAddr, params()->range.size());
 
-    pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE,
-                                MAP_ANON | MAP_PRIVATE, -1, 0);
+    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
+        PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
 
     if (pmemAddr == (void *)MAP_FAILED) {
         perror("mmap");
@@ -504,12 +503,14 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
         fatal("Unable to malloc memory to read file %s\n", filename);
 
     /* Only copy bytes that are non-zero, so we don't give the VM system hell */
-    while (curSize < params()->addrRange.size()) {
+    while (curSize < params()->range.size()) {
         bytesRead = gzread(compressedMem, tempPage, chunkSize);
-        if (bytesRead != chunkSize && bytesRead != params()->addrRange.size() - curSize)
+        if (bytesRead != chunkSize &&
+            bytesRead != params()->range.size() - curSize)
             fatal("Read failed on physical memory checkpoint file '%s'"
                   " got %d bytes, expected %d or %d bytes\n",
-                  filename, bytesRead, chunkSize, params()->addrRange.size()-curSize);
+                  filename, bytesRead, chunkSize,
+                  params()->range.size() - curSize);
 
         assert(bytesRead % sizeof(long) == 0);
 
@@ -531,33 +532,8 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
 
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-    Param<string> file;
-    Param<Range<Addr> > range;
-    Param<Tick> latency;
-    Param<bool> zero;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-    INIT_PARAM_DFLT(file, "memory mapped file", ""),
-    INIT_PARAM(range, "Device Address Range"),
-    INIT_PARAM(latency, "Memory access latency"),
-    INIT_PARAM(zero, "Zero initialize memory")
-
-END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-CREATE_SIM_OBJECT(PhysicalMemory)
+PhysicalMemory *
+PhysicalMemoryParams::create()
 {
-    PhysicalMemory::Params *p = new PhysicalMemory::Params;
-    p->name = getInstanceName();
-    p->addrRange = range;
-    p->latency = latency;
-    p->zero = zero;
-    return new PhysicalMemory(p);
+    return new PhysicalMemory(this);
 }
-
-REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 8b13d32c1..b06cc90f8 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -34,13 +34,15 @@
 #ifndef __PHYSICAL_MEMORY_HH__
 #define __PHYSICAL_MEMORY_HH__
 
+#include <map>
+#include <string>
+
 #include "base/range.hh"
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/tport.hh"
+#include "params/PhysicalMemory.hh"
 #include "sim/eventq.hh"
-#include <map>
-#include <string>
 
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
@@ -149,25 +151,20 @@ class PhysicalMemory : public MemObject
 
   public:
     Addr new_page();
-    uint64_t size() { return params()->addrRange.size(); }
-    uint64_t start() { return params()->addrRange.start; }
-
-    struct Params
-    {
-        std::string name;
-        Range<Addr> addrRange;
-        Tick latency;
-        bool zero;
-    };
-
-  protected:
-    Params *_params;
+    uint64_t size() { return params()->range.size(); }
+    uint64_t start() { return params()->range.start; }
 
   public:
-    const Params *params() const { return _params; }
-    PhysicalMemory(Params *p);
+    typedef PhysicalMemoryParams Params;
+    PhysicalMemory(const Params *p);
     virtual ~PhysicalMemory();
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
   public:
     int deviceBlockSize();
     void getAddressRanges(AddrRangeList &resp, bool &snoop);