style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

11 files changed, 76 insertions, 76 deletions

diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 127c547ac..9bfbd646d 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -38,8 +38,8 @@
 #include <list>
 
 #include "base/printable.hh"
-#include "sim/core.hh"		// for Tick
-#include "arch/isa_traits.hh"	// for Addr
+#include "sim/core.hh"          // for Tick
+#include "arch/isa_traits.hh"   // for Addr
 #include "mem/packet.hh"
 #include "mem/request.hh"
 
@@ -48,17 +48,17 @@
  */
 enum CacheBlkStatusBits {
     /** valid, readable */
-    BlkValid =		0x01,
+    BlkValid =          0x01,
     /** write permission */
-    BlkWritable =	0x02,
+    BlkWritable =       0x02,
     /** read permission (yes, block can be valid but not readable) */
-    BlkReadable =	0x04,
+    BlkReadable =       0x04,
     /** dirty (modified) */
-    BlkDirty =		0x08,
+    BlkDirty =          0x08,
     /** block was referenced */
-    BlkReferenced =	0x10,
+    BlkReferenced =     0x10,
     /** block was a hardware prefetch yet unaccessed*/
-    BlkHWPrefetched =	0x20
+    BlkHWPrefetched =   0x20
 };
 
 /**
@@ -108,8 +108,8 @@ class CacheBlk
      */
     class Lock {
       public:
-        int cpuNum;	// locking CPU
-        int threadNum;	// locking thread ID within CPU
+        int cpuNum;     // locking CPU
+        int threadNum;  // locking thread ID within CPU
 
         // check for matching execution context
         bool matchesContext(Request *req)
diff --git a/src/mem/cache/builder.cc b/src/mem/cache/builder.cc
index db900c64c..97930fe60 100644
--- a/src/mem/cache/builder.cc
+++ b/src/mem/cache/builder.cc
@@ -100,101 +100,101 @@ using namespace TheISA;
         return retval;                                                  \
     } while (0)
 
-#define BUILD_CACHE_PANIC(x) do {			\
-        panic("%s not compiled into M5", x);		\
+#define BUILD_CACHE_PANIC(x) do {                       \
+        panic("%s not compiled into M5", x);            \
     } while (0)
 
 #if defined(USE_CACHE_FALRU)
-#define BUILD_FALRU_CACHE do {			    \
+#define BUILD_FALRU_CACHE do {                              \
         FALRU *tags = new FALRU(block_size, size, latency); \
-        BUILD_CACHE(FALRU, tags);		\
+        BUILD_CACHE(FALRU, tags);                           \
     } while (0)
 #else
 #define BUILD_FALRU_CACHE BUILD_CACHE_PANIC("falru cache")
 #endif
 
 #if defined(USE_CACHE_LRU)
-#define BUILD_LRU_CACHE do {				\
-        LRU *tags = new LRU(numSets, block_size, assoc, latency);	\
-        BUILD_CACHE(LRU, tags);			\
+#define BUILD_LRU_CACHE do {                                            \
+        LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
+        BUILD_CACHE(LRU, tags);                                         \
     } while (0)
 #else
 #define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
 #endif
 
 #if defined(USE_CACHE_SPLIT)
-#define BUILD_SPLIT_CACHE do {					\
+#define BUILD_SPLIT_CACHE do {                                                \
         Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
-                                two_queue, latency);		\
-        BUILD_CACHE(Split, tags);			\
+                                two_queue, latency);                          \
+        BUILD_CACHE(Split, tags);                                             \
     } while (0)
 #else
 #define BUILD_SPLIT_CACHE BUILD_CACHE_PANIC("split cache")
 #endif
 
 #if defined(USE_CACHE_SPLIT_LIFO)
-#define BUILD_SPLIT_LIFO_CACHE do {				\
+#define BUILD_SPLIT_LIFO_CACHE do {                                     \
         SplitLIFO *tags = new SplitLIFO(block_size, size, assoc,        \
-                                        latency, two_queue, -1);	\
-        BUILD_CACHE(SplitLIFO, tags);			\
+                                        latency, two_queue, -1);        \
+        BUILD_CACHE(SplitLIFO, tags);                                   \
     } while (0)
 #else
 #define BUILD_SPLIT_LIFO_CACHE BUILD_CACHE_PANIC("lifo cache")
 #endif
 
 #if defined(USE_CACHE_IIC)
-#define BUILD_IIC_CACHE do {			\
-        IIC *tags = new IIC(iic_params);		\
-        BUILD_CACHE(IIC, tags);	\
+#define BUILD_IIC_CACHE do {                            \
+        IIC *tags = new IIC(iic_params);                \
+        BUILD_CACHE(IIC, tags);                         \
     } while (0)
 #else
 #define BUILD_IIC_CACHE BUILD_CACHE_PANIC("iic")
 #endif
 
-#define BUILD_CACHES do {				\
-        if (repl == NULL) {				\
-            if (numSets == 1) {				\
-                BUILD_FALRU_CACHE;		\
-            } else {					\
-                if (split == true) {			\
-                    BUILD_SPLIT_CACHE;		\
-                } else if (lifo == true) {		\
-                    BUILD_SPLIT_LIFO_CACHE;	\
-                } else {				\
-                    BUILD_LRU_CACHE;		\
-                }					\
-            }						\
-        } else {					\
-            BUILD_IIC_CACHE;			\
-        }						\
+#define BUILD_CACHES do {                               \
+        if (repl == NULL) {                             \
+            if (numSets == 1) {                         \
+                BUILD_FALRU_CACHE;                      \
+            } else {                                    \
+                if (split == true) {                    \
+                    BUILD_SPLIT_CACHE;                  \
+                } else if (lifo == true) {              \
+                    BUILD_SPLIT_LIFO_CACHE;             \
+                } else {                                \
+                    BUILD_LRU_CACHE;                    \
+                }                                       \
+            }                                           \
+        } else {                                        \
+            BUILD_IIC_CACHE;                            \
+        }                                               \
     } while (0)
 
-#define BUILD_COHERENCE(b) do {						\
+#define BUILD_COHERENCE(b) do {                                         \
     } while (0)
 
 #if defined(USE_TAGGED)
-#define BUILD_TAGGED_PREFETCHER(t)                              \
+#define BUILD_TAGGED_PREFETCHER(t)                                      \
     pf = new TaggedPrefetcher(this)
 #else
 #define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
 #endif
 
 #if defined(USE_STRIDED)
-#define BUILD_STRIDED_PREFETCHER(t)                             \
+#define BUILD_STRIDED_PREFETCHER(t)                                     \
     pf = new StridePrefetcher(this)
 #else
 #define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
 #endif
 
 #if defined(USE_GHB)
-#define BUILD_GHB_PREFETCHER(t)                         \
+#define BUILD_GHB_PREFETCHER(t)                                         \
     pf = new GHBPrefetcher(this)
 #else
 #define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
 #endif
 
 #if defined(USE_TAGGED)
-#define BUILD_NULL_PREFETCHER(t)                                \
+#define BUILD_NULL_PREFETCHER(t)                                        \
     pf = new TaggedPrefetcher(this)
 #else
 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index b116b66c7..e93058d6e 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -40,12 +40,12 @@ void
 StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
                                     std::list<Tick> &delays)
 {
-//	Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
+//      Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
     int cpuID = pkt->req->getCpuNum();
     if (!useCPUId) cpuID = 0;
 
     /* Scan Table for IAddr Match */
-/*	std::list<strideEntry*>::iterator iter;
+/*      std::list<strideEntry*>::iterator iter;
   for (iter=table[cpuID].begin();
   iter !=table[cpuID].end();
   iter++) {
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index f6bdbc424..ca173277c 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -50,7 +50,7 @@ class StridePrefetcher : public BasePrefetcher
         int stride;
         int64_t confidence;
 
-/*	bool operator < (strideEntry a,strideEntry b)
+/*      bool operator < (strideEntry a,strideEntry b)
         {
             if (a.confidence == b.confidence) {
                 return true; //??????
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 2825599f6..af9a75d43 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -365,7 +365,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
         tag_ptr->refCount = 0;
 
         if (tag_ptr->isDirty()) {
-/*	    PacketPtr writeback =
+/*          PacketPtr writeback =
                 buildWritebackReq(regenerateBlkAddr(tag_ptr->tag, 0),
                                   tag_ptr->req->asid, tag_ptr->xc, blkSize,
                                   tag_ptr->data,
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 7f352e9c4..7fb5318a0 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -113,7 +113,7 @@ LRU::LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency) :
     // allocate data storage in one big chunk
     dataBlks = new uint8_t[numSets*assoc*blkSize];
 
-    blkIndex = 0;	// index into blks array
+    blkIndex = 0;       // index into blks array
     for (i = 0; i < numSets; ++i) {
         sets[i].assoc = assoc;
 
@@ -160,7 +160,7 @@ LRU::probe(Addr addr) const
 
     LRUBlk *blk = sets[myset].findBlk(tag);
 
-    return (blk != NULL);	// true if in cache
+    return (blk != NULL);       // true if in cache
 }
 
 LRUBlk*
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index ea5606cde..65be492de 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -127,7 +127,7 @@ public:
      * @param _assoc The associativity of the cache.
      * @param _hit_latency The latency in cycles for a hit.
      */
-    LRU(int _numSets, int _blkSize,	int _assoc, int _hit_latency);
+    LRU(int _numSets, int _blkSize,     int _assoc, int _hit_latency);
 
     /**
      * Destructor
diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc
index bcccdcb30..2b01b07cd 100644
--- a/src/mem/cache/tags/split_lru.cc
+++ b/src/mem/cache/tags/split_lru.cc
@@ -113,7 +113,7 @@ SplitLRU::SplitLRU(int _numSets, int _blkSize, int _assoc, int _hit_latency, int
     // allocate data storage in one big chunk
     dataBlks = new uint8_t[numSets*assoc*blkSize];
 
-    blkIndex = 0;	// index into blks array
+    blkIndex = 0;       // index into blks array
     for (i = 0; i < numSets; ++i) {
         sets[i].assoc = assoc;
 
@@ -179,7 +179,7 @@ SplitLRU::probe(Addr addr) const
 
     SplitBlk *blk = sets[myset].findBlk(tag);
 
-    return (blk != NULL);	// true if in cache
+    return (blk != NULL);       // true if in cache
 }
 
 SplitBlk*
diff --git a/src/mem/dram.cc b/src/mem/dram.cc
index 75146f9ed..ff01ab1dc 100644
--- a/src/mem/dram.cc
+++ b/src/mem/dram.cc
@@ -366,7 +366,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
   int lat=0, temp=0, current_bank=0;
   int current_row=0, current_device=0;
 
-  int was_miss = 0;	// determines if there was an active row miss this access
+  int was_miss = 0;     // determines if there was an active row miss this access
 
   //md_addr_t physic_address; /* linear memory address to be accessed */
   Addr physic_address; /* linear memory address to be accessed */
@@ -415,7 +415,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
         int SD_BEST_T_WRITE_WRITE_OBANK = 0; /* WAW, row miss/hit, another bank */
 
     Tick time_since_last_access = curTick-time_last_access;
-    Tick time_last_miss = 0;	// used for keeping track of times between activations (page misses)
+    Tick time_last_miss = 0;    // used for keeping track of times between activations (page misses)
     //int was_idle = (curTick > busy_until);
         bool srow_flag = false;
         int timing_correction = 0;
@@ -433,7 +433,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
         // SDRAM does not use the active_row array in closed_page mode
         // TODO: handle closed page operation
 
-    } else {		// DRDRAM uses the active_row array
+    } else {            // DRDRAM uses the active_row array
         for( int i = 0; i < bank_max; i++ ) {
                 if( (active_row[current_bank] != row_max)) all_precharged = 0;
         }
@@ -923,7 +923,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
           }
         // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
         // if((_cpu_num < num_cpus) && (_cpu_num >= 0))
-    //	bank_access_profile[_cpu_num][current_bank]++;
+    //  bank_access_profile[_cpu_num][current_bank]++;
 
         return lat;
       }
@@ -2034,7 +2034,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
 
         // if((_cpu_num < num_cpus) && (_cpu_num >= 0))
                 // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
-    //	bank_access_profile[_cpu_num][current_bank]++;
+    //  bank_access_profile[_cpu_num][current_bank]++;
         return lat;
       }
 
@@ -2226,7 +2226,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
         /*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick, overlap, lat);debug*/
         // if((_cpu_num < num_cpus) && (_cpu_num >= 0))
                 // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
-    //	bank_access_profile[_cpu_num][current_bank]++;
+    //  bank_access_profile[_cpu_num][current_bank]++;
         return lat;
       }
 
@@ -2468,7 +2468,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
 
         // if((_cpu_num < num_cpus) && (_cpu_num >= 0))
                 // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
-    //	bank_access_profile[_cpu_num][current_bank]++;
+    //  bank_access_profile[_cpu_num][current_bank]++;
         return lat;
       }
 
@@ -2525,7 +2525,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
 
         // if((_cpu_num < num_cpus) && (_cpu_num >= 0))
                 // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
-    //	bank_access_profile[_cpu_num][current_bank]++;
+    //  bank_access_profile[_cpu_num][current_bank]++;
         return lat;
       }
 
@@ -2593,7 +2593,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
           }
         // if((_cpu_num < num_cpus) && (_cpu_num >= 0))
                 // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
-    //	bank_access_profile[_cpu_num][current_bank]++;
+    //  bank_access_profile[_cpu_num][current_bank]++;
         return lat;
       }
 
@@ -2608,7 +2608,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
         assert(chunks >0);
         // if((_cpu_num < num_cpus) && (_cpu_num >= 0))
                 // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
-    //	bank_access_profile[_cpu_num][current_bank]++;
+    //  bank_access_profile[_cpu_num][current_bank]++;
         return(/* first chunk latency */act_lat +
                (/* remainder chunk latency */cas_lat * (chunks - 1)));
       }
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index ceb36b5c0..2a0086ba9 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -89,9 +89,9 @@ class PhysicalMemory : public MemObject
 
         static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
 
-        Addr addr; 	// locked address
-        int cpuNum;	// locking CPU
-        int threadNum;	// locking thread ID within CPU
+        Addr addr;      // locked address
+        int cpuNum;     // locking CPU
+        int threadNum;  // locking thread ID within CPU
 
         // check for matching execution context
         bool matchesContext(Request *req)
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 85ff8a445..ab8f9d596 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -53,21 +53,21 @@ typedef Request* RequestPtr;
 /** ASI information for this request if it exsits. */
 const uint32_t ASI_BITS         = 0x000FF;
 /** The request is a Load locked/store conditional. */
-const uint32_t LOCKED		= 0x00100;
+const uint32_t LOCKED           = 0x00100;
 /** The virtual address is also the physical address. */
-const uint32_t PHYSICAL		= 0x00200;
+const uint32_t PHYSICAL         = 0x00200;
 /** The request is an ALPHA VPTE pal access (hw_ld). */
-const uint32_t VPTE		= 0x00400;
+const uint32_t VPTE             = 0x00400;
 /** Use the alternate mode bits in ALPHA. */
-const uint32_t ALTMODE		= 0x00800;
+const uint32_t ALTMODE          = 0x00800;
 /** The request is to an uncacheable address. */
-const uint32_t UNCACHEABLE	= 0x01000;
+const uint32_t UNCACHEABLE      = 0x01000;
 /** The request should not cause a page fault. */
 const uint32_t NO_FAULT         = 0x02000;
 /** The request should be prefetched into the exclusive state. */
-const uint32_t PF_EXCLUSIVE	= 0x10000;
+const uint32_t PF_EXCLUSIVE     = 0x10000;
 /** The request should be marked as LRU. */
-const uint32_t EVICT_NEXT	= 0x20000;
+const uint32_t EVICT_NEXT       = 0x20000;
 /** The request should ignore unaligned access faults */
 const uint32_t NO_ALIGN_FAULT   = 0x40000;
 /** The request was an instruction read. */