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authorAndreas Hansson <andreas.hansson@arm.com>2016-02-23 03:27:20 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2016-02-23 03:27:20 -0500
commit4619f0ee8bf2cd3f05f727b56c1e449b4bfecce1 (patch)
tree8a3a8f1938cce3fab1b897ba7fb32d45e481f2e1 /src/mem
parent5a88f0931fa1e222ed3ac3aff4046721c593ee3e (diff)
downloadgem5-4619f0ee8bf2cd3f05f727b56c1e449b4bfecce1.tar.xz
scons: Add missing override to appease clang
Make clang happy...again.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/ruby/system/DMASequencer.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 9cf187c83..3b408e5ac 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -56,11 +56,11 @@ class DMASequencer : public RubyPort
void init() override;
/* external interface */
- RequestStatus makeRequest(PacketPtr pkt);
+ RequestStatus makeRequest(PacketPtr pkt) override;
bool busy() { return m_is_busy;}
- int outstandingCount() const { return (m_is_busy ? 1 : 0); }
- bool isDeadlockEventScheduled() const { return false; }
- void descheduleDeadlockEvent() {}
+ int outstandingCount() const override { return (m_is_busy ? 1 : 0); }
+ bool isDeadlockEventScheduled() const override { return false; }
+ void descheduleDeadlockEvent() override {}
/* SLICC callback */
void dataCallback(const DataBlock & dblk);