summaryrefslogtreecommitdiff
path: root/src/mem
diff options
context:
space:
mode:
authorSteve Reinhardt <stever@gmail.com>2008-08-03 18:13:29 -0400
committerSteve Reinhardt <stever@gmail.com>2008-08-03 18:13:29 -0400
commit62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch)
tree739253709735d1a8b5da963d2230a5418779d297 /src/mem
parentb179c3f4cd1e89872de34d70105f703e72377029 (diff)
downloadgem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/PhysicalMemory.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py
index e512cea1c..95cc73daa 100644
--- a/src/mem/PhysicalMemory.py
+++ b/src/mem/PhysicalMemory.py
@@ -35,7 +35,7 @@ class PhysicalMemory(MemObject):
port = VectorPort("the access port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
- latency = Param.Latency('1t', "latency of an access")
+ latency = Param.Latency('30ns', "latency of an access")
latency_var = Param.Latency('0ns', "access variablity")
zero = Param.Bool(False, "zero initialize memory")
null = Param.Bool(False, "do not store data, always return zero")