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authorRon Dreslinski <rdreslin@umich.edu>2006-07-10 17:16:15 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-07-10 17:16:15 -0400
commit6592045cbc138306474d24d60daa222a07673fe2 (patch)
tree5fb86438978286223db6f4a9faf47a516d9d3d6b /src/mem
parent5584e2b26eccb5d2bf445b8b0b2040449d0b0a77 (diff)
downloadgem5-6592045cbc138306474d24d60daa222a07673fe2.tar.xz
Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu
src/mem/cache/base_cache.cc: If we still have outstanding requests, need to schedule event again src/mem/cache/miss/miss_queue.cc: Need to use block size so overlapping requests match in the MSHR's src/mem/cache/miss/mshr.cc: Actually save the address, otherwise we can't match MSHR's --HG-- extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/base_cache.cc17
-rw-r--r--src/mem/cache/miss/miss_queue.cc8
-rw-r--r--src/mem/cache/miss/mshr.cc1
3 files changed, 20 insertions, 6 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index be9769fdc..451da28e8 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -117,11 +117,24 @@ BaseCache::CacheEvent::process()
if (!pkt)
{
if (!cachePort->isCpuSide)
+ {
pkt = cachePort->cache->getPacket();
+ bool success = cachePort->sendTiming(pkt);
+ DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
+ pkt->getAddr(), success ? "succesful" : "unsuccesful");
+ cachePort->cache->sendResult(pkt, success);
+ if (success && cachePort->cache->doMasterRequest())
+ {
+ //Still more to issue, rerequest in 1 cycle
+ pkt = NULL;
+ this->schedule(curTick+1);
+ }
+ }
else
+ {
pkt = cachePort->cache->getCoherencePacket();
- bool success = cachePort->sendTiming(pkt);
- cachePort->cache->sendResult(pkt, success);
+ cachePort->sendTiming(pkt);
+ }
return;
}
//Know the packet to send, no need to mark in service (must succed)
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index da0448ad3..4a3dc1062 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
MSHR*
MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
{
- MSHR* mshr = mq.allocate(pkt, size);
+ MSHR* mshr = mq.allocate(pkt, blkSize);
mshr->order = order++;
if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
// Mark this as a cache line fill
@@ -372,7 +372,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
MSHR*
MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
{
- MSHR* mshr = wb.allocate(pkt,pkt->getSize());
+ MSHR* mshr = wb.allocate(pkt,blkSize);
mshr->order = order++;
//REMOVING COMPRESSION FOR NOW
@@ -446,11 +446,11 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
/**
* @todo Add write merging here.
*/
- mshr = allocateWrite(pkt, pkt->getSize(), time);
+ mshr = allocateWrite(pkt, blkSize, time);
return;
}
- mshr = allocateMiss(pkt, size, time);
+ mshr = allocateMiss(pkt, blkSize, time);
}
MSHR*
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 1a85d3018..db2f40c56 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -57,6 +57,7 @@ void
MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
Packet * &target)
{
+ addr = _addr;
if (target)
{
//Have a request, just use it