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authorSteve Reinhardt <stever@eecs.umich.edu>2007-05-22 06:29:48 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-05-22 06:29:48 -0700
commit9048c695a0ecde709a074259bad9ad1cda57a303 (patch)
treea7f029ca6b30b538c5089b06d1ab0e255efda26b /src/mem
parent0a02e3a7643d15ed662aedf4566a9dea7a07f2f2 (diff)
downloadgem5-9048c695a0ecde709a074259bad9ad1cda57a303.tar.xz
Another pass of minor changes in preparation for new protocol.
src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: Get rid of old invalidate propagation logic in preparation for new multilevel snoop protocol. src/mem/cache/coherence/coherence_protocol.cc: L2 cache now has protocol, so protocol must handle ReadExReq coming in from the CPU side. src/mem/cache/miss/mshr_queue.cc: Assertion is failing, so let's take it out for now. src/mem/packet.cc: src/mem/packet.hh: Add WritebackAck command. Reorganize enum to put responses next to corresponding requests. Get rid of unused WriteReqNoAck. --HG-- extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/cache_impl.hh17
-rw-r--r--src/mem/cache/coherence/coherence_protocol.cc3
-rw-r--r--src/mem/cache/coherence/simple_coherence.hh6
-rw-r--r--src/mem/cache/miss/mshr_queue.cc1
-rw-r--r--src/mem/packet.cc11
-rw-r--r--src/mem/packet.hh4
6 files changed, 13 insertions, 29 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 6b9eac865..56352c110 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -794,14 +794,7 @@ Cache<TagStore,Coherence>::snoop(PacketPtr &pkt)
return;
}
- //Send a timing (true) invalidate up if the protocol calls for it
- if (coherence->propogateInvalidate(pkt, true)) {
- //Temp hack, we had a functional read hit in the L1, mark as success
- pkt->flags |= SATISFIED;
- pkt->result = Packet::Success;
- respondToSnoop(pkt, curTick + hitLatency);
- return;
- }
+ ///// PROPAGATE SNOOP UPWARD HERE
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt->getAddr());
@@ -1097,13 +1090,7 @@ template<class TagStore, class Coherence>
Tick
Cache<TagStore,Coherence>::snoopProbe(PacketPtr &pkt)
{
- //Send a atomic (false) invalidate up if the protocol calls for it
- if (coherence->propogateInvalidate(pkt, false)) {
- //Temp hack, we had a functional read hit in the L1, mark as success
- pkt->flags |= SATISFIED;
- pkt->result = Packet::Success;
- return hitLatency;
- }
+ ///// PROPAGATE SNOOP UPWARD HERE
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt->getAddr());
diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc
index 33a8a4e63..bc8de0d26 100644
--- a/src/mem/cache/coherence/coherence_protocol.cc
+++ b/src/mem/cache/coherence/coherence_protocol.cc
@@ -295,11 +295,14 @@ CoherenceProtocol::CoherenceProtocol(const string &name,
tt[Invalid][MC::ReadReq].onRequest(MC::ReadReq);
// we only support write allocate right now
tt[Invalid][MC::WriteReq].onRequest(MC::ReadExReq);
+ tt[Invalid][MC::ReadExReq].onRequest(MC::ReadExReq);
tt[Invalid][MC::SwapReq].onRequest(MC::ReadExReq);
tt[Shared][MC::WriteReq].onRequest(writeToSharedCmd);
+ tt[Shared][MC::ReadExReq].onRequest(MC::ReadExReq);
tt[Shared][MC::SwapReq].onRequest(writeToSharedCmd);
if (hasOwned) {
tt[Owned][MC::WriteReq].onRequest(writeToSharedCmd);
+ tt[Owned][MC::ReadExReq].onRequest(MC::ReadExReq);
tt[Owned][MC::SwapReq].onRequest(writeToSharedCmd);
}
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index 1c89c703a..095260ca4 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -161,12 +161,6 @@ class SimpleCoherence
bool allowFastWrites() { return false; }
bool hasProtocol() { return true; }
-
- bool propogateInvalidate(PacketPtr pkt, bool isTiming)
- {
- //For now we do nothing, asssumes simple coherence is top level of cache
- return false;
- }
};
#endif //__SIMPLE_COHERENCE_HH__
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index add11dfe7..e9aa89bf8 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -119,7 +119,6 @@ MSHRQueue::allocate(PacketPtr &pkt, int size)
if (!pkt->needsResponse()) {
mshr->allocateAsBuffer(pkt);
} else {
- assert(size !=0);
mshr->allocate(pkt->cmd, aligned_addr, size, pkt);
allocatedTargets += 1;
}
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 2463a19ba..8c69def37 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -56,17 +56,18 @@ MemCmd::commandInfo[] =
{ 0, InvalidCmd, "InvalidCmd" },
/* ReadReq */
{ SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" },
+ /* ReadResp */
+ { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" },
/* WriteReq */
{ SET4(IsWrite, IsRequest, NeedsResponse, HasData),
WriteResp, "WriteReq" },
- /* WriteReqNoAck */
- { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "WriteReqNoAck" },
- /* ReadResp */
- { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" },
/* WriteResp */
{ SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" },
/* Writeback */
- { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "Writeback" },
+ { SET4(IsWrite, IsRequest, HasData, NeedsResponse),
+ WritebackAck, "Writeback" },
+ /* WritebackAck */
+ { SET2(IsWrite, IsResponse), InvalidCmd, "WritebackAck" },
/* SoftPFReq */
{ SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse),
SoftPFResp, "SoftPFReq" },
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 577f99116..413ffa26b 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -73,11 +73,11 @@ class MemCmd
{
InvalidCmd,
ReadReq,
- WriteReq,
- WriteReqNoAck,
ReadResp,
+ WriteReq,
WriteResp,
Writeback,
+ WritebackAck,
SoftPFReq,
HardPFReq,
SoftPFResp,