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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-12 08:35:49 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-12 08:35:49 -0400 |
commit | c9634d9b38e5d58a8b68af5f26c257886d791518 (patch) | |
tree | c3687d14ad34bfc6bbb21999f7c85921dd26bd31 /src/mem | |
parent | 15ca4f2fc7c81bb3ade68cbff7d58bd01aa00d33 (diff) | |
download | gem5-c9634d9b38e5d58a8b68af5f26c257886d791518.tar.xz |
Ruby: Ensure order-dependent iteration uses an ordered map
This patch fixes a bug in Ruby that caused non-deterministic
simulation when changing the underlying hash map implementation. The
reason is order-dependent behaviour in combination with iteration over
the hash map contents. The two locations where a sorted container is
assumed are now changed to make use of a std::map instead of the
unordered hash map.
With this change, the stats changes slightly and the follow-on
changeset will update the relevant statistics.
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/ruby/buffers/MessageBuffer.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/system/TimerTable.hh | 6 | ||||
-rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 2 |
3 files changed, 8 insertions, 4 deletions
diff --git a/src/mem/ruby/buffers/MessageBuffer.hh b/src/mem/ruby/buffers/MessageBuffer.hh index dc9fb1a9e..0000aef16 100644 --- a/src/mem/ruby/buffers/MessageBuffer.hh +++ b/src/mem/ruby/buffers/MessageBuffer.hh @@ -162,7 +162,9 @@ class MessageBuffer Consumer* m_consumer_ptr; // Consumer to signal a wakeup(), can be NULL std::vector<MessageBufferNode> m_prio_heap; - typedef m5::hash_map< Address, std::list<MsgPtr> > StallMsgMapType; + // use a std::map for the stalled messages as this container is + // sorted and ensures a well-defined iteration order + typedef std::map< Address, std::list<MsgPtr> > StallMsgMapType; typedef std::vector<MsgPtr>::iterator MsgListIter; StallMsgMapType m_stall_msg_map; diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh index f78d93956..41b4ea68d 100644 --- a/src/mem/ruby/system/TimerTable.hh +++ b/src/mem/ruby/system/TimerTable.hh @@ -33,7 +33,6 @@ #include <iostream> #include <string> -#include "base/hashmap.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" @@ -74,7 +73,10 @@ class TimerTable TimerTable& operator=(const TimerTable& obj); // Data Members (m_prefix) - typedef m5::hash_map<Address, Time> AddressMap; + + // use a std::map for the address map as this container is sorted + // and ensures a well-defined iteration order + typedef std::map<Address, Time> AddressMap; AddressMap m_map; mutable bool m_next_valid; mutable Time m_next_time; // Only valid if m_next_valid is true diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 7d863e349..a9886b229 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -324,7 +324,7 @@ MachineID m_machineID; bool m_is_blocking; std::map<Address, MessageBuffer*> m_block_map; typedef std::vector<MessageBuffer*> MsgVecType; -typedef m5::hash_map< Address, MsgVecType* > WaitingBufType; +typedef std::map< Address, MsgVecType* > WaitingBufType; WaitingBufType m_waiting_buffers; int m_max_in_port_rank; int m_cur_in_port_rank; |