Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0756f7f1f63fae472e0ef1d20e9eb38e56de78c8

2 files changed, 36 insertions, 5 deletions

diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index b5cecc7da..a34a0393a 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -54,6 +54,9 @@ PageTable::PageTable(System *_system, Addr _pageSize)
       system(_system)
 {
     assert(isPowerOf2(pageSize));
+    pTableCache[0].vaddr = 0;
+    pTableCache[1].vaddr = 0;
+    pTableCache[2].vaddr = 0;
 }
 
 PageTable::~PageTable()
@@ -95,7 +98,7 @@ PageTable::allocate(Addr vaddr, int size)
     assert(pageOffset(vaddr) == 0);
 
     for (; size > 0; size -= pageSize, vaddr += pageSize) {
-        std::map<Addr,Addr>::iterator iter = pTable.find(vaddr);
+        m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
 
         if (iter != pTable.end()) {
             // already mapped
@@ -103,6 +106,12 @@ PageTable::allocate(Addr vaddr, int size)
         }
 
         pTable[vaddr] = system->new_page();
+        pTableCache[2].paddr = pTableCache[1].paddr;
+        pTableCache[2].vaddr = pTableCache[1].vaddr;
+        pTableCache[1].paddr = pTableCache[0].paddr;
+        pTableCache[1].vaddr = pTableCache[0].vaddr;
+        pTableCache[0].paddr = pTable[vaddr];
+        pTableCache[0].vaddr = vaddr;
     }
 }
 
@@ -112,7 +121,22 @@ bool
 PageTable::translate(Addr vaddr, Addr &paddr)
 {
     Addr page_addr = pageAlign(vaddr);
-    std::map<Addr,Addr>::iterator iter = pTable.find(page_addr);
+    paddr = 0;
+
+    if (pTableCache[0].vaddr == vaddr) {
+        paddr = pTableCache[0].paddr;
+        return true;
+    }
+    if (pTableCache[1].vaddr == vaddr) {
+        paddr = pTableCache[1].paddr;
+        return true;
+    }
+    if (pTableCache[2].vaddr == vaddr) {
+        paddr = pTableCache[2].paddr;
+        return true;
+    }
+
+    m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
 
     if (iter == pTable.end()) {
         return false;
@@ -130,7 +154,7 @@ PageTable::translate(RequestPtr &req)
     assert(pageAlign(req->getVaddr() + req->getSize() - 1)
            == pageAlign(req->getVaddr()));
     if (!translate(req->getVaddr(), paddr)) {
-        return genMachineCheckFault();
+        return genPageTableFault(req->getVaddr());
     }
     req->setPaddr(paddr);
     return page_check(req->getPaddr(), req->getSize());
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index f7212d423..494c0ce9a 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -37,9 +37,9 @@
 #define __PAGE_TABLE__
 
 #include <string>
-#include <map>
 
 #include "arch/isa_traits.hh"
+#include "base/hashmap.hh"
 #include "base/trace.hh"
 #include "mem/request.hh"
 #include "mem/packet.hh"
@@ -53,7 +53,14 @@ class System;
 class PageTable
 {
   protected:
-    std::map<Addr,Addr> pTable;
+    m5::hash_map<Addr,Addr> pTable;
+
+    struct cacheElement {
+        Addr paddr;
+        Addr vaddr;
+    } ;
+
+    struct cacheElement pTableCache[3];
 
     const Addr pageSize;
     const Addr offsetMask;