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authorRon Dreslinski <rdreslin@umich.edu>2006-10-20 13:04:59 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-20 13:04:59 -0400
commit54ed57cc4c0aab92cd5b3727c9def7667a49669d (patch)
tree9717a13c28584bfa6980df8246ca6c0ee7c5f342 /src/mem
parenta4c6f0d69eda5d23b12576080d532ddf768fbdbe (diff)
parent28e9641c2cf063d8ee1eba9f440dfcda9c82d965 (diff)
downloadgem5-54ed57cc4c0aab92cd5b3727c9def7667a49669d.tar.xz
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest src/mem/tport.cc: Merge PacketPtr changes --HG-- extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/base_cache.cc27
-rw-r--r--src/mem/cache/cache_impl.hh63
-rw-r--r--src/mem/packet.cc2
-rw-r--r--src/mem/tport.cc6
4 files changed, 8 insertions, 90 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 6cbeef5a4..0694aae6e 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -115,32 +115,7 @@ BaseCache::CachePort::recvFunctional(PacketPtr pkt)
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt)) {
- uint8_t* pkt_data;
- uint8_t* write_data;
- int data_size;
- if (target->getAddr() < pkt->getAddr()) {
- int offset = pkt->getAddr() - target->getAddr();
- pkt_data = pkt->getPtr<uint8_t>();
- write_data = target->getPtr<uint8_t>() + offset;
- data_size = target->getSize() - offset;
- assert(data_size > 0);
- if (data_size > pkt->getSize())
- data_size = pkt->getSize();
- } else {
- int offset = target->getAddr() - pkt->getAddr();
- pkt_data = pkt->getPtr<uint8_t>() + offset;
- write_data = target->getPtr<uint8_t>();
- data_size = pkt->getSize() - offset;
- assert(data_size >= pkt->getSize());
- if (data_size > target->getSize())
- data_size = target->getSize();
- }
-
- if (pkt->isWrite()) {
- memcpy(pkt_data, write_data, data_size);
- } else {
- memcpy(write_data, pkt_data, data_size);
- }
+ fixPacket(pkt, target);
}
}
cache->doFunctionalAccess(pkt, isCpuSide);
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index dcb0e7b78..66a9ee554 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -560,7 +560,6 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
if (!update) {
// Check for data in MSHR and writebuffer.
if (mshr) {
- warn("Found outstanding miss on an non-update probe");
MSHR::TargetList *targets = mshr->getTargetList();
MSHR::TargetList::iterator i = targets->begin();
MSHR::TargetList::iterator end = targets->end();
@@ -568,71 +567,15 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
- if (target->isWrite() && target->intersect(pkt)) {
- uint8_t* pkt_data;
- uint8_t* write_data;
- int data_size;
- if (target->getAddr() < pkt->getAddr()) {
- int offset = pkt->getAddr() - target->getAddr();
- pkt_data = pkt->getPtr<uint8_t>();
- write_data = target->getPtr<uint8_t>() + offset;
- data_size = target->getSize() - offset;
- assert(data_size > 0);
- if (data_size > pkt->getSize())
- data_size = pkt->getSize();
- } else {
- int offset = target->getAddr() - pkt->getAddr();
- pkt_data = pkt->getPtr<uint8_t>() + offset;
- write_data = target->getPtr<uint8_t>();
- data_size = pkt->getSize() - offset;
- assert(data_size >= pkt->getSize());
- if (data_size > target->getSize())
- data_size = target->getSize();
- }
-
- if (pkt->isWrite()) {
- memcpy(pkt_data, write_data, data_size);
- } else {
- pkt->flags |= SATISFIED;
- pkt->result = Packet::Success;
- memcpy(write_data, pkt_data, data_size);
- }
+ if (target->intersect(pkt)) {
+ fixPacket(pkt, target);
}
}
}
for (int i = 0; i < writes.size(); ++i) {
PacketPtr write = writes[i]->pkt;
if (write->intersect(pkt)) {
- warn("Found outstanding write on an non-update probe");
- uint8_t* pkt_data;
- uint8_t* write_data;
- int data_size;
- if (write->getAddr() < pkt->getAddr()) {
- int offset = pkt->getAddr() - write->getAddr();
- pkt_data = pkt->getPtr<uint8_t>();
- write_data = write->getPtr<uint8_t>() + offset;
- data_size = write->getSize() - offset;
- assert(data_size > 0);
- if (data_size > pkt->getSize())
- data_size = pkt->getSize();
- } else {
- int offset = write->getAddr() - pkt->getAddr();
- pkt_data = pkt->getPtr<uint8_t>() + offset;
- write_data = write->getPtr<uint8_t>();
- data_size = pkt->getSize() - offset;
- assert(data_size >= pkt->getSize());
- if (data_size > write->getSize())
- data_size = write->getSize();
- }
-
- if (pkt->isWrite()) {
- memcpy(pkt_data, write_data, data_size);
- } else {
- pkt->flags |= SATISFIED;
- pkt->result = Packet::Success;
- memcpy(write_data, pkt_data, data_size);
- }
-
+ fixPacket(pkt, write);
}
}
if (pkt->isRead()
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 834f4b63c..fa8d82c46 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -151,7 +151,7 @@ fixPacket(PacketPtr func, PacketPtr timing)
Addr timingStart = timing->getAddr();
Addr timingEnd = timing->getAddr() + timing->getSize() - 1;
- assert(!(funcStart > timingEnd || timingStart < funcEnd));
+ assert(!(funcStart > timingEnd || timingStart > funcEnd));
if (DTRACE(FunctionalAccess)) {
DebugOut() << func;
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 350b4c8e3..5c5aaa3da 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -33,12 +33,11 @@
void
SimpleTimingPort::recvFunctional(PacketPtr pkt)
{
- //First check queued events
std::list<PacketPtr>::iterator i = transmitList.begin();
std::list<PacketPtr>::iterator end = transmitList.end();
bool cont = true;
- while (i != end && cont) {
+ while (i != end) {
PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
@@ -46,8 +45,9 @@ SimpleTimingPort::recvFunctional(PacketPtr pkt)
fixPacket(pkt, target);
}
+
//Then just do an atomic access and throw away the returned latency
- if (cont)
+ if (pkt->result != Packet::Success)
recvAtomic(pkt);
}