mem: different HMC configuration

In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.

Highlights

1- It explores 3 different HMC architectures

2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This  will connect vaults to serial links

3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports

4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink

Committed by Jason Lowe-Power <jason@lowepower.com>

3 files changed, 14 insertions, 6 deletions

diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index f05f2872d..fd9b0ff6b 100644
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -61,3 +61,5 @@ class SerialLink(MemObject):
     #  link belongs to and the number of lanes:
     num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
         "link. (aka. lane width)")
+    link_speed = Param.UInt64(1, "Gb/s Speed of each parallel lane inside the"
+        "serial link. (aka. lane speed)")
diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc
index b6cb097b7..25f5291bb 100644
--- a/src/mem/serial_link.cc
+++ b/src/mem/serial_link.cc
@@ -87,7 +87,9 @@ SerialLink::SerialLink(SerialLinkParams *p)
                 ticksToCycles(p->delay), p->resp_size, p->ranges),
       masterPort(p->name + ".master", *this, slavePort,
                  ticksToCycles(p->delay), p->req_size),
-      num_lanes(p->num_lanes)
+      num_lanes(p->num_lanes),
+      link_speed(p->link_speed)
+
 {
 }
 
@@ -153,8 +155,9 @@ SerialLink::SerialLinkMasterPort::recvTimingResp(PacketPtr pkt)
     // have to wait to receive the whole packet. So we only account for the
     // deserialization latency.
     Cycles cycles = delay;
-    cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes));
-    Tick t = serial_link.clockEdge(cycles);
+    cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes
+                * serial_link.link_speed));
+     Tick t = serial_link.clockEdge(cycles);
 
     //@todo: If the processor sends two uncached requests towards HMC and the
     // second one is smaller than the first one. It may happen that the second
@@ -214,7 +217,7 @@ SerialLink::SerialLinkSlavePort::recvTimingReq(PacketPtr pkt)
             // only.
             Cycles cycles = delay;
             cycles += Cycles(divCeil(pkt->getSize() * 8,
-                serial_link.num_lanes));
+                    serial_link.num_lanes * serial_link.link_speed));
             Tick t = serial_link.clockEdge(cycles);
 
             //@todo: If the processor sends two uncached requests towards HMC
@@ -301,7 +304,7 @@ SerialLink::SerialLinkMasterPort::trySendTiming()
 
             // Make sure bandwidth limitation is met
             Cycles cycles = Cycles(divCeil(pkt->getSize() * 8,
-                serial_link.num_lanes));
+                serial_link.num_lanes * serial_link.link_speed));
             Tick t = serial_link.clockEdge(cycles);
             serial_link.schedule(sendEvent, std::max(next_req.tick, t));
         }
@@ -346,7 +349,7 @@ SerialLink::SerialLinkSlavePort::trySendTiming()
 
             // Make sure bandwidth limitation is met
             Cycles cycles = Cycles(divCeil(pkt->getSize() * 8,
-                serial_link.num_lanes));
+                serial_link.num_lanes * serial_link.link_speed));
             Tick t = serial_link.clockEdge(cycles);
             serial_link.schedule(sendEvent, std::max(next_resp.tick, t));
         }
diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh
index d4f6ca488..9fbcce335 100644
--- a/src/mem/serial_link.hh
+++ b/src/mem/serial_link.hh
@@ -312,6 +312,9 @@ class SerialLink : public MemObject
     /** Number of parallel lanes in this serial link */
     unsigned num_lanes;
 
+    /** Speed of each link (Gb/s) in this serial link */
+    uint64_t link_speed;
+
   public:
 
     virtual BaseMasterPort& getMasterPort(const std::string& if_name,