mem-cache: Add support for checking whether a cache is busy

This changeset adds support for checking whether the cache is
currently busy and a timing request would be rejected.

Change-Id: I5e37b011b2387b1fa1c9e687b9be545f06ffb5f5
Reviewed-on: https://gem5-review.googlesource.com/5042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

2 files changed, 20 insertions, 13 deletions

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 2a3dddc19..bd1318fb9 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -2542,30 +2542,35 @@ Cache::CpuSidePort::getAddrRanges() const
 }
 
 bool
-Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
+Cache::CpuSidePort::tryTiming(PacketPtr pkt)
 {
     assert(!cache->system->bypassCaches());
 
-    bool success = false;
+    // always let express snoop packets through if even if blocked
+    if (pkt->isExpressSnoop()) {
+        return true;
+    } else if (isBlocked() || mustSendRetry) {
+        // either already committed to send a retry, or blocked
+        mustSendRetry = true;
+        return false;
+    }
+    mustSendRetry = false;
+    return true;
+}
+
+bool
+Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
+{
+    assert(!cache->system->bypassCaches());
 
     // always let express snoop packets through if even if blocked
     if (pkt->isExpressSnoop()) {
-        // do not change the current retry state
         bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
         assert(bypass_success);
         return true;
-    } else if (blocked || mustSendRetry) {
-        // either already committed to send a retry, or blocked
-        success = false;
-    } else {
-        // pass it on to the cache, and let the cache decide if we
-        // have to retry or not
-        success = cache->recvTimingReq(pkt);
     }
 
-    // remember if we have to retry
-    mustSendRetry = !success;
-    return success;
+    return tryTiming(pkt) && cache->recvTimingReq(pkt);
 }
 
 Tick
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index a39a9c740..790c685f4 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -90,6 +90,8 @@ class Cache : public BaseCache
 
         virtual bool recvTimingSnoopResp(PacketPtr pkt);
 
+        virtual bool tryTiming(PacketPtr pkt);
+
         virtual bool recvTimingReq(PacketPtr pkt);
 
         virtual Tick recvAtomic(PacketPtr pkt);