diff options
| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-06 09:28:16 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-06 09:28:16 -0400 |
| commit | c42a7bc4f6c03703e17fb55afe5ba8e2d920e5d5 (patch) | |
| tree | d43eb581e9ef48cc9114bd7cfc5f49851409bc12 /src/mem | |
| parent | dfdb683fb9b1ebb10e80228df6494ea482609518 (diff) | |
| parent | 48e89a9d1eb186cce8bc0fab76c28730896b491a (diff) | |
| download | gem5-c42a7bc4f6c03703e17fb55afe5ba8e2d920e5d5.tar.xz | |
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 2f1bbe84c92879fd1bfa579adc62a367ece1cddd
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 228cd2d73..00fecc2b7 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -51,7 +51,7 @@ #include "mem/cache/miss/mshr.hh" #include "mem/cache/prefetch/prefetcher.hh" -#include "sim/sim_events.hh" // for SimExitEvent +#include "sim/sim_exit.hh" // for SimExitEvent template<class TagStore, class Buffering, class Coherence> bool @@ -263,7 +263,7 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt) if (missCount) { --missCount; if (missCount == 0) - new SimLoopExitEvent(curTick, "A cache reached the maximum miss count"); + exitSimLoop("A cache reached the maximum miss count"); } } missQueue->handleMiss(pkt, size, curTick + hitLatency); |