summaryrefslogtreecommitdiff
path: root/src/mem
diff options
context:
space:
mode:
authorRon Dreslinski <rdreslin@umich.edu>2006-07-07 15:15:11 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-07-07 15:15:11 -0400
commitea11c7bdbefc8eb640f875cdf91a6d6bed398ec4 (patch)
tree3af6e347d31fffe724122db63ebff97aaf819c3e /src/mem
parent1ccfdb442ff34f9f2b38ee7716b7baee99a397c2 (diff)
downloadgem5-ea11c7bdbefc8eb640f875cdf91a6d6bed398ec4.tar.xz
Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory
configs/test/test.py: Update to use new cpu getPort functionality src/cpu/base.cc: Make cpu's a memObject to expose getPort interface src/cpu/base.hh: Make cpu's a memObject to export getPort interface src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Now use the connector via getPort interface src/mem/cache/base_cache.cc: Make sure the cache recognizes all port names --HG-- extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/base_cache.cc8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 4fbda4074..b2caca765 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -144,7 +144,13 @@ BaseCache::getPort(const std::string &if_name, int idx)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
return cpuSidePort;
}
- if (if_name == "functional")
+ else if (if_name == "functional")
+ {
+ if(cpuSidePort == NULL)
+ cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+ return cpuSidePort;
+ }
+ else if (if_name == "cpu_side")
{
if(cpuSidePort == NULL)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);