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authorAndreas Hansson <andreas.hansson@arm.com>2012-07-09 12:35:34 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-07-09 12:35:34 -0400
commit46d9adb68c96b94ae25bbe92d34e375daf532ece (patch)
tree8a0792d1d67958eeb65ee978edc5217e2b499ae7 /src/mem
parent830391cad9764b923edd8f761e9fe5d11fd9d837 (diff)
downloadgem5-46d9adb68c96b94ae25bbe92d34e375daf532ece.tar.xz
Port: Make getAddrRanges const
This patch makes getAddrRanges const throughout the code base. There is no reason why it should not be, and making it const prevents adding any unintentional side-effects.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/bridge.cc2
-rw-r--r--src/mem/bridge.hh2
-rw-r--r--src/mem/bus.cc16
-rw-r--r--src/mem/bus.hh5
-rw-r--r--src/mem/cache/cache.hh2
-rw-r--r--src/mem/cache/cache_impl.hh2
-rw-r--r--src/mem/coherent_bus.hh2
-rw-r--r--src/mem/comm_monitor.cc2
-rw-r--r--src/mem/comm_monitor.hh4
-rw-r--r--src/mem/noncoherent_bus.hh2
-rw-r--r--src/mem/port.hh3
-rw-r--r--src/mem/ruby/system/RubyPort.cc2
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
-rw-r--r--src/mem/simple_mem.cc2
-rw-r--r--src/mem/simple_mem.hh2
15 files changed, 26 insertions, 24 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index eabfbc44d..3a5313e7b 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -443,7 +443,7 @@ Bridge::BridgeMasterPort::checkFunctional(PacketPtr pkt)
}
AddrRangeList
-Bridge::BridgeSlavePort::getAddrRanges()
+Bridge::BridgeSlavePort::getAddrRanges() const
{
return ranges;
}
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index 4595cf516..eefb4d121 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -276,7 +276,7 @@ class Bridge : public MemObject
/** When receiving a address range request the peer port,
pass it to the bridge. */
- virtual AddrRangeList getAddrRanges();
+ virtual AddrRangeList getAddrRanges() const;
};
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 5be53dbcd..2e735e03b 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -269,7 +269,7 @@ BaseBus::findPort(Addr addr)
return dest_id;
// Check normal port ranges
- PortIter i = portMap.find(RangeSize(addr,1));
+ PortMapConstIter i = portMap.find(RangeSize(addr,1));
if (i != portMap.end()) {
dest_id = i->second;
updatePortCache(dest_id, i->first.start, i->first.end);
@@ -278,8 +278,8 @@ BaseBus::findPort(Addr addr)
// Check if this matches the default range
if (useDefaultRange) {
- AddrRangeIter a_end = defaultRange.end();
- for (AddrRangeIter i = defaultRange.begin(); i != a_end; i++) {
+ AddrRangeConstIter a_end = defaultRange.end();
+ for (AddrRangeConstIter i = defaultRange.begin(); i != a_end; i++) {
if (*i == addr) {
DPRINTF(BusAddrRanges, " found addr %#llx on default\n",
addr);
@@ -332,7 +332,7 @@ BaseBus::recvRangeChange(PortID master_port_id)
MasterPort *port = masterPorts[master_port_id];
// Clean out any previously existent ids
- for (PortIter portIter = portMap.begin();
+ for (PortMapIter portIter = portMap.begin();
portIter != portMap.end(); ) {
if (portIter->second == master_port_id)
portMap.erase(portIter++);
@@ -367,22 +367,22 @@ BaseBus::recvRangeChange(PortID master_port_id)
}
AddrRangeList
-BaseBus::getAddrRanges()
+BaseBus::getAddrRanges() const
{
AddrRangeList ranges;
DPRINTF(BusAddrRanges, "received address range request, returning:\n");
- for (AddrRangeIter dflt_iter = defaultRange.begin();
+ for (AddrRangeConstIter dflt_iter = defaultRange.begin();
dflt_iter != defaultRange.end(); dflt_iter++) {
ranges.push_back(*dflt_iter);
DPRINTF(BusAddrRanges, " -- Dflt: %#llx : %#llx\n",dflt_iter->start,
dflt_iter->end);
}
- for (PortIter portIter = portMap.begin();
+ for (PortMapConstIter portIter = portMap.begin();
portIter != portMap.end(); portIter++) {
bool subset = false;
- for (AddrRangeIter dflt_iter = defaultRange.begin();
+ for (AddrRangeConstIter dflt_iter = defaultRange.begin();
dflt_iter != defaultRange.end(); dflt_iter++) {
if ((portIter->first.start < dflt_iter->start &&
portIter->first.end >= dflt_iter->start) ||
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 4f0e44b1c..94068d897 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -85,7 +85,8 @@ class BaseBus : public MemObject
Event * drainEvent;
- typedef range_map<Addr, PortID>::iterator PortIter;
+ typedef range_map<Addr, PortID>::iterator PortMapIter;
+ typedef range_map<Addr, PortID>::const_iterator PortMapConstIter;
range_map<Addr, PortID> portMap;
AddrRangeList defaultRange;
@@ -187,7 +188,7 @@ class BaseBus : public MemObject
*
* @return a list of non-overlapping address ranges
*/
- AddrRangeList getAddrRanges();
+ AddrRangeList getAddrRanges() const;
/** Calculate the timing parameters for the packet. Updates the
* firstWordTime and finishTime fields of the packet object.
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index beb3903da..9bdbd3456 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -101,7 +101,7 @@ class Cache : public BaseCache
virtual unsigned deviceBlockSize() const
{ return cache->getBlockSize(); }
- virtual AddrRangeList getAddrRanges();
+ virtual AddrRangeList getAddrRanges() const;
public:
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index cc68bbd3d..f7901261f 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1588,7 +1588,7 @@ Cache<TagStore>::unserialize(Checkpoint *cp, const std::string &section)
template<class TagStore>
AddrRangeList
-Cache<TagStore>::CpuSidePort::getAddrRanges()
+Cache<TagStore>::CpuSidePort::getAddrRanges() const
{
return cache->getAddrRanges();
}
diff --git a/src/mem/coherent_bus.hh b/src/mem/coherent_bus.hh
index a8737eeed..460afd828 100644
--- a/src/mem/coherent_bus.hh
+++ b/src/mem/coherent_bus.hh
@@ -124,7 +124,7 @@ class CoherentBus : public BaseBus
/**
* Return the union of all adress ranges seen by this bus.
*/
- virtual AddrRangeList getAddrRanges()
+ virtual AddrRangeList getAddrRanges() const
{ return bus.getAddrRanges(); }
/**
diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc
index 8469a2469..1b030de5e 100644
--- a/src/mem/comm_monitor.cc
+++ b/src/mem/comm_monitor.cc
@@ -345,7 +345,7 @@ CommMonitor::deviceBlockSizeSlave()
}
AddrRangeList
-CommMonitor::getAddrRanges()
+CommMonitor::getAddrRanges() const
{
// get the address ranges of the connected slave port
return masterPort.getAddrRanges();
diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh
index 54f9690ed..4b90306e1 100644
--- a/src/mem/comm_monitor.hh
+++ b/src/mem/comm_monitor.hh
@@ -230,7 +230,7 @@ class CommMonitor : public MemObject
return mon.deviceBlockSizeSlave();
}
- AddrRangeList getAddrRanges()
+ AddrRangeList getAddrRanges() const
{
return mon.getAddrRanges();
}
@@ -269,7 +269,7 @@ class CommMonitor : public MemObject
unsigned deviceBlockSizeSlave();
- AddrRangeList getAddrRanges();
+ AddrRangeList getAddrRanges() const;
bool isSnooping() const;
diff --git a/src/mem/noncoherent_bus.hh b/src/mem/noncoherent_bus.hh
index 7227d3bc6..46fc65fad 100644
--- a/src/mem/noncoherent_bus.hh
+++ b/src/mem/noncoherent_bus.hh
@@ -120,7 +120,7 @@ class NoncoherentBus : public BaseBus
/**
* Return the union of all adress ranges seen by this bus.
*/
- virtual AddrRangeList getAddrRanges()
+ virtual AddrRangeList getAddrRanges() const
{ return bus.getAddrRanges(); }
/**
diff --git a/src/mem/port.hh b/src/mem/port.hh
index cfeb87571..35f2993df 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -64,6 +64,7 @@
typedef std::list<Range<Addr> > AddrRangeList;
typedef std::list<Range<Addr> >::iterator AddrRangeIter;
+typedef std::list<Range<Addr> >::const_iterator AddrRangeConstIter;
class MemObject;
@@ -379,7 +380,7 @@ class SlavePort : public Port
*
* @return a list of ranges responded to
*/
- virtual AddrRangeList getAddrRanges() = 0;
+ virtual AddrRangeList getAddrRanges() const = 0;
protected:
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 285017a06..a6eb4d22d 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -669,7 +669,7 @@ RubyPort::PioPort::sendNextCycle(PacketPtr pkt)
}
AddrRangeList
-RubyPort::M5Port::getAddrRanges()
+RubyPort::M5Port::getAddrRanges() const
{
// at the moment the assumption is that the master does not care
AddrRangeList ranges;
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 8833efb6e..3b19632e2 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -86,7 +86,7 @@ class RubyPort : public MemObject
virtual bool recvTimingReq(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
- virtual AddrRangeList getAddrRanges();
+ virtual AddrRangeList getAddrRanges() const;
private:
bool isPhysMemAddress(Addr addr);
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 10e809d0b..aa9168bf7 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -132,7 +132,7 @@ SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
{ }
AddrRangeList
-SimpleMemory::MemoryPort::getAddrRanges()
+SimpleMemory::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
ranges.push_back(memory.getAddrRange());
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index b21b38fd8..5f136ed51 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -77,7 +77,7 @@ class SimpleMemory : public AbstractMemory
virtual void recvFunctional(PacketPtr pkt);
- virtual AddrRangeList getAddrRanges();
+ virtual AddrRangeList getAddrRanges() const;
};