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| author | Derek Hower <drh5@cs.wisc.edu> | 2009-09-15 09:47:11 -0500 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2009-09-15 09:47:11 -0500 |
| commit | 803cf3b434d4b92e01bc0c73fcaff9b69685ef11 (patch) | |
| tree | fbb6f26c441ed3974add274ea2a83890ef86bd77 /src/mem | |
| parent | 11f3f8306847bf912a9c5a31186231d23b31030d (diff) | |
| download | gem5-803cf3b434d4b92e01bc0c73fcaff9b69685ef11.tar.xz | |
ruby: made configuration parameters uniform
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/ruby/config/MESI_CMP_directory.rb | 4 | ||||
| -rw-r--r-- | src/mem/ruby/config/defaults.rb | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/ruby/config/MESI_CMP_directory.rb b/src/mem/ruby/config/MESI_CMP_directory.rb index 4d9ff30b3..7a9d47f24 100644 --- a/src/mem/ruby/config/MESI_CMP_directory.rb +++ b/src/mem/ruby/config/MESI_CMP_directory.rb @@ -12,8 +12,8 @@ class MESI_CMP_directory_L2CacheController < CacheController def argv() vec = super() vec += " cache " + cache.obj_name - vec += " l2_request_latency "+l2_request_latency.to_s - vec += " l2_response_latency "+l2_response_latency.to_s + vec += " l2_request_latency "+request_latency.to_s + vec += " l2_response_latency "+response_latency.to_s vec += " to_l1_latency "+to_L1_latency.to_s return vec end diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb index 20d633d87..fd19e92b6 100644 --- a/src/mem/ruby/config/defaults.rb +++ b/src/mem/ruby/config/defaults.rb @@ -160,8 +160,8 @@ class MOESI_CMP_directory_DMAController < DMAController end class MESI_CMP_directory_L2CacheController < CacheController - default_param :l2_request_latency, Integer, 2 - default_param :l2_response_latency, Integer, 2 + default_param :request_latency, Integer, 2 + default_param :response_latency, Integer, 2 default_param :to_L1_latency, Integer, 1 #if 0 then automatically calculated |