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authorNikos Nikoleris <nikos.nikoleris@arm.com>2018-02-05 17:44:51 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2018-03-30 19:01:51 +0000
commit430bef385983db08bb1dd131f6b0ab5ca6d66fbe (patch)
treeee7d2f281cb8fab5c81b8df0e3a0f616c5c93756 /src/mem
parent83f88cd1c0f27adb4704b374541bd6aff7e3e3fb (diff)
downloadgem5-430bef385983db08bb1dd131f6b0ab5ca6d66fbe.tar.xz
mem-cache: Remove unused return value from the recvTimingReq func
The recvTimingReq function in the cache always returns true. This changeset removes the return value. Change-Id: I00dddca65ee7224ecfa579ea5195c841dac02972 Reviewed-on: https://gem5-review.googlesource.com/8289 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/cache.cc16
-rw-r--r--src/mem/cache/cache.hh3
2 files changed, 7 insertions, 12 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index cbc0ed90a..c03b5b2a8 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -648,7 +648,7 @@ Cache::promoteWholeLineWrites(PacketPtr pkt)
}
}
-bool
+void
Cache::recvTimingReq(PacketPtr pkt)
{
DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
@@ -660,7 +660,7 @@ Cache::recvTimingReq(PacketPtr pkt)
// @todo This should really enqueue the packet rather
bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
assert(success);
- return true;
+ return;
}
promoteWholeLineWrites(pkt);
@@ -730,7 +730,7 @@ Cache::recvTimingReq(PacketPtr pkt)
// and we have already sent out any express snoops in the
// section above to ensure all other copies in the system are
// invalidated
- return true;
+ return;
}
// anything that is merely forwarded pays for the forward latency and
@@ -976,8 +976,6 @@ Cache::recvTimingReq(PacketPtr pkt)
if (next_pf_time != MaxTick)
schedMemSideSendEvent(next_pf_time);
-
- return true;
}
PacketPtr
@@ -2770,13 +2768,11 @@ Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
assert(!cache->system->bypassCaches());
// always let express snoop packets through if even if blocked
- if (pkt->isExpressSnoop()) {
- bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
- assert(bypass_success);
+ if (pkt->isExpressSnoop() || tryTiming(pkt)) {
+ cache->recvTimingReq(pkt);
return true;
}
-
- return tryTiming(pkt) && cache->recvTimingReq(pkt);
+ return false;
}
Tick
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4d840be27..7d282790f 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -350,9 +350,8 @@ class Cache : public BaseCache
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The result of the access.
*/
- bool recvTimingReq(PacketPtr pkt);
+ void recvTimingReq(PacketPtr pkt);
/**
* Insert writebacks into the write buffer