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authorGabe Black <gblack@eecs.umich.edu>2006-08-15 05:07:15 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-08-15 05:07:15 -0400
commit74546aac0124a5ba09a0e6bfef18dc3e0b7509b8 (patch)
tree367e2fbfa58d670c2a91076f080c998e69f4eeb6 /src/mem
parent741bc40cc336be6afdff73a230eaec980812b7d5 (diff)
downloadgem5-74546aac0124a5ba09a0e6bfef18dc3e0b7509b8.tar.xz
Cleaned up include files and got rid of many using directives in header files.
--HG-- extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/cache_impl.hh4
-rw-r--r--src/mem/cache/miss/blocking_buffer.cc2
-rw-r--r--src/mem/cache/prefetch/tagged_prefetcher_impl.hh1
-rw-r--r--src/mem/packet.hh2
-rw-r--r--src/mem/page_table.hh2
-rw-r--r--src/mem/port_impl.hh6
-rw-r--r--src/mem/request.hh2
7 files changed, 7 insertions, 12 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a447ae3d5..56e7a4d58 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -53,8 +53,6 @@
#include "sim/sim_events.hh" // for SimExitEvent
-using namespace std;
-
template<class TagStore, class Buffering, class Coherence>
bool
Cache<TagStore,Buffering,Coherence>::
@@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
// There can be many matching outstanding writes.
- vector<MSHR*> writes;
+ std::vector<MSHR*> writes;
missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
if (!update) {
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index 10d53b109..2f61e8a54 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -40,8 +40,6 @@
#include "sim/eventq.hh" // for Event declaration.
#include "mem/request.hh"
-using namespace TheISA;
-
/**
* @todo Move writebacks into shared BaseBuffer class.
*/
diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
index db5c94820..e554b3cec 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
@@ -33,6 +33,7 @@
* Describes a tagged prefetcher based on template policies.
*/
+#include "arch/isa_traits.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
template <class TagStore, class Buffering>
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 534db0077..83b4006e2 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -39,7 +39,7 @@
#define __MEM_PACKET_HH__
#include "mem/request.hh"
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
#include "sim/root.hh"
#include <list>
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 86247f276..52c81671b 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -38,7 +38,7 @@
#include <string>
-#include "arch/faults.hh"
+#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "base/hashmap.hh"
#include "base/trace.hh"
diff --git a/src/mem/port_impl.hh b/src/mem/port_impl.hh
index e9a159293..b7980bdd2 100644
--- a/src/mem/port_impl.hh
+++ b/src/mem/port_impl.hh
@@ -28,8 +28,6 @@
* Authors: Ali Saidi
*/
-#include "arch/isa_specific.hh"
-#include "arch/isa_traits.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
@@ -37,7 +35,7 @@ template <typename T>
void
FunctionalPort::writeHtoG(Addr addr, T d)
{
- d = TheISA::htog(d);
+ d = htog(d);
writeBlob(addr, (uint8_t*)&d, sizeof(T));
}
@@ -48,6 +46,6 @@ FunctionalPort::readGtoH(Addr addr)
{
T d;
readBlob(addr, (uint8_t*)&d, sizeof(T));
- return TheISA::gtoh(d);
+ return gtoh(d);
}
diff --git a/src/mem/request.hh b/src/mem/request.hh
index a62fe2a20..f3647e55f 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -38,7 +38,7 @@
#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
#include "sim/root.hh"
class Request;