diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-03-19 14:17:48 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-03-19 14:17:48 -0700 |
commit | dd9083115ed3f1ee297c2ff7255fdd3fee276e7a (patch) | |
tree | b23d52b1c3c7f87d4aa4967cc11d86ce728d02ed /src/mem | |
parent | 541fa1091a42b5148bc98d25ca50f9206226e025 (diff) | |
download | gem5-dd9083115ed3f1ee297c2ff7255fdd3fee276e7a.tar.xz |
MOESI_hammer: minor fixes to full-bit dir
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/protocol/MOESI_hammer-dir.sm | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index 0bc863afb..369f8784b 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -186,7 +186,7 @@ machine(Directory, "AMD Hammer-like protocol") } PfEntry getProbeFilterEntry(Address addr), return_by_pointer="yes" { - if(probe_filter_enabled) { + if (probe_filter_enabled || full_bit_dir_enabled) { PfEntry pfEntry := static_cast(PfEntry, "pointer", probeFilter.lookup(addr)); return pfEntry; } @@ -200,8 +200,6 @@ machine(Directory, "AMD Hammer-like protocol") if (probe_filter_enabled || full_bit_dir_enabled) { if (is_valid(pf_entry)) { assert(pf_entry.PfState == getDirectoryEntry(addr).DirectoryState); - } else { - assert(getDirectoryEntry(addr).DirectoryState == State:E); } } return getDirectoryEntry(addr).DirectoryState; @@ -219,6 +217,9 @@ machine(Directory, "AMD Hammer-like protocol") if (state == State:NX || state == State:NO || state == State:S || state == State:O) { assert(is_valid(pf_entry)); } + if (state == State:E) { + assert(is_valid(pf_entry) == false); + } } if (state == State:E || state == State:NX || state == State:NO || state == State:S || state == State:O) { @@ -469,6 +470,7 @@ machine(Directory, "AMD Hammer-like protocol") peek(requestQueue_in, RequestMsg) { set_cache_entry(probeFilter.allocate(address, new PfEntry)); cache_entry.Owner := in_msg.Requestor; + cache_entry.Sharers.setSize(machineCount(MachineType:L1Cache)); } } } |