Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920

4 files changed, 19 insertions, 12 deletions

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 0c1f384b1..ffd5e25a7 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -115,11 +115,14 @@ void Bus::occupyBus(PacketPtr pkt)
     //Bring tickNextIdle up to the present tick
     //There is some potential ambiguity where a cycle starts, which might make
     //a difference when devices are acting right around a cycle boundary. Using
-    //a < allows things which happen exactly on a cycle boundary to take up only
-    //the following cycle. Anthing that happens later will have to "wait" for
-    //the end of that cycle, and then start using the bus after that.
-    while (tickNextIdle < curTick)
-        tickNextIdle += clock;
+    //a < allows things which happen exactly on a cycle boundary to take up
+    //only the following cycle. Anything that happens later will have to "wait"
+    //for the end of that cycle, and then start using the bus after that.
+    if (tickNextIdle < curTick) {
+        tickNextIdle = curTick;
+        if (tickNextIdle % clock != 0)
+            tickNextIdle = curTick - (curTick % clock) + clock;
+    }
 
     // The packet will be sent. Figure out how long it occupies the bus, and
     // how much of that time is for the first "word", aka bus width.
@@ -132,10 +135,9 @@ void Bus::occupyBus(PacketPtr pkt)
         // We're using the "adding instead of dividing" trick again here
         if (pkt->hasData()) {
             int dataSize = pkt->getSize();
-            for (int transmitted = 0; transmitted < dataSize;
-                    transmitted += width) {
+            numCycles += dataSize/width;
+            if (dataSize % width)
                 numCycles++;
-            }
         } else {
             // If the packet didn't have data, it must have been a response.
             // Those use the bus for one cycle to send their data.
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 32f3f0174..55b68f81f 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -90,3 +90,4 @@ class BaseCache(MemObject):
          "Only prefetch on data not on instruction accesses")
     cpu_side = Port("Port on side closer to CPU")
     mem_side = Port("Port on side closer to MEM")
+    addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 6291b7c1d..80da045ef 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -43,6 +43,7 @@
 #include <bitset>
 
 #include "base/compiler.hh"
+#include "base/fast_alloc.hh"
 #include "base/misc.hh"
 #include "mem/request.hh"
 #include "sim/host.hh"
@@ -177,7 +178,7 @@ class MemCmd
  * ultimate destination and back, possibly being conveyed by several
  * different Packets along the way.)
  */
-class Packet
+class Packet : public FastAlloc
 {
   public:
 
@@ -257,7 +258,7 @@ class Packet
     /** A virtual base opaque structure used to hold coherence-related
      *    state.  A specific subclass would be derived from this to
      *    carry state specific to a particular coherence protocol.  */
-    class CoherenceState {
+    class CoherenceState : public FastAlloc {
       public:
         virtual ~CoherenceState() {}
     };
@@ -274,7 +275,7 @@ class Packet
      *    needed to process it.  A specific subclass would be derived
      *    from this to carry state specific to a particular sending
      *    device.  */
-    class SenderState {
+    class SenderState : public FastAlloc {
       public:
         virtual ~SenderState() {}
     };
diff --git a/src/mem/request.hh b/src/mem/request.hh
index d2ebc91d3..e08593f0d 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -39,6 +39,7 @@
 #ifndef __MEM_REQUEST_HH__
 #define __MEM_REQUEST_HH__
 
+#include "base/fast_alloc.hh"
 #include "sim/host.hh"
 #include "sim/core.hh"
 
@@ -76,7 +77,7 @@ const uint32_t MEM_SWAP         = 0x100000;
 const uint32_t MEM_SWAP_COND    = 0x200000;
 
 
-class Request
+class Request : public FastAlloc
 {
   private:
     /**
@@ -153,6 +154,8 @@ class Request
         setVirt(_asid, _vaddr, _size, _flags, _pc);
     }
 
+    ~Request() {}  // for FastAlloc
+
     /**
      * Set up CPU and thread numbers. */
     void setThreadContext(int _cpuNum, int _threadNum)