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authorAlexandru Dutu <alexandru.dutu@amd.com>2016-02-06 17:21:20 -0800
committerAlexandru Dutu <alexandru.dutu@amd.com>2016-02-06 17:21:20 -0800
commit0f27d70e90c20ba21d3f6a3360a11d9d5e9ee133 (patch)
treeb9d33a3e92e6d20e5f82d238bf6e94dfc4e2301e /src/mem
parent5200e04e92b487181d4a678231564272730e04a2 (diff)
downloadgem5-0f27d70e90c20ba21d3f6a3360a11d9d5e9ee133.tar.xz
x86: revamp cmpxchg8b/cmpxchg16b implementation
The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b.
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