Do a functional access to levels above on a read as a temporary solution for L2's in FS

Fix a small writeback bug when missing in the L2 in atomic mode

src/mem/bus.cc:
    Fix a comment to make sense
src/mem/cache/cache_impl.hh:
    Do a functional access to levels above on a read as a temporary solution for L2's in FS
    Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
    Update ref's for writeback changes

--HG--
extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251

5 files changed, 55 insertions, 9 deletions

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 6b5b63f50..e9a870b80 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -296,7 +296,7 @@ Bus::findPort(Addr addr, int id)
 
 
     // we shouldn't be sending this back to where it came from
-    // only on a functional access and then we should terminate
+    // do the snoop access and then we should terminate
     // the cyclical call.
     if (dest_id == id)
         return 0;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index df59b0a4f..3a681bc52 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -391,7 +391,13 @@ Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
     }
 
     //Send a timing (true) invalidate up if the protocol calls for it
-    coherence->propogateInvalidate(pkt, true);
+    if (coherence->propogateInvalidate(pkt, true)) {
+        //Temp hack, we had a functional read hit in the L1, mark as success
+        pkt->flags |= SATISFIED;
+        pkt->result = Packet::Success;
+        respondToSnoop(pkt, curTick + hitLatency);
+        return;
+    }
 
     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
     BlkType *blk = tags->findBlock(pkt);
@@ -562,6 +568,7 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
 
     PacketList writebacks;
     int lat;
+
     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 
     DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(),
@@ -615,7 +622,8 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
             // Can't handle it, return request unsatisfied.
             panic("Atomic access ran into outstanding MSHR's or WB's!");
         }
-        if (!pkt->req->isUncacheable()) {
+        if (!pkt->req->isUncacheable() /*Uncacheables just go through*/
+            && (pkt->cmd != Packet::Writeback)/*Writebacks on miss fall through*/) {
                 // Fetch the cache block to fill
             BlkType *blk = tags->findBlock(pkt);
             Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
@@ -691,7 +699,12 @@ Tick
 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 {
     //Send a atomic (false) invalidate up if the protocol calls for it
-    coherence->propogateInvalidate(pkt, false);
+    if (coherence->propogateInvalidate(pkt, false)) {
+        //Temp hack, we had a functional read hit in the L1, mark as success
+        pkt->flags |= SATISFIED;
+        pkt->result = Packet::Success;
+        return hitLatency;
+    }
 
     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
     BlkType *blk = tags->findBlock(pkt);
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index 5316e64b9..a1fd33080 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -161,10 +161,10 @@ class SimpleCoherence
 
     bool hasProtocol() { return true; }
 
-    void propogateInvalidate(PacketPtr pkt, bool isTiming)
+    bool propogateInvalidate(PacketPtr pkt, bool isTiming)
     {
         //For now we do nothing, asssumes simple coherence is top level of cache
-        return;
+        return false;
     }
 };
 
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 19230e35b..5813a0281 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -54,6 +54,7 @@ UniCoherence::sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
     {
         bool unblock = cshrs.isFull();
 //        cshrs.markInService(cshr);
+        delete pkt->req;
         cshrs.deallocate(cshr);
         if (!cshrs.havePending()) {
             cache->clearSlaveRequest(Request_Coherence);
@@ -81,17 +82,28 @@ UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
     }
     else if (blk) {
         new_state = blk->status;
+        if (pkt->isRead()) {
+            DPRINTF(Cache, "Uni-coherence snoops a read that hit in itself"
+                    ". Should satisfy the packet\n");
+            return true; //Satisfy Reads if we can
+        }
     }
     return false;
 }
 
-void
+bool
 UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
 {
+    //Make sure we don't snoop a write
+    //we are expecting writeInvalidates on the snoop port of a uni-coherent cache
+    assert(!(!pkt->isInvalidate() && pkt->isWrite()));
+
     if (pkt->isInvalidate()) {
+/*  Temp Fix for now, forward all invalidates up as functional accesses */
         if (isTiming) {
             // Forward to other caches
-            PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+            Request* req = new Request(pkt->req->getPaddr(), pkt->getSize(), 0);
+            PacketPtr tmp = new Packet(req, Packet::InvalidateReq, -1);
             cshrs.allocate(tmp);
             cache->setSlaveRequest(Request_Coherence, curTick);
             if (cshrs.isFull())
@@ -102,5 +114,26 @@ UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
             cache->cpuSidePort->sendAtomic(tmp);
             delete tmp;
         }
+/**/
+/*            PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+            cache->cpuSidePort->sendFunctional(tmp);
+            delete tmp;
+*/
+    }
+    if (pkt->isRead()) {
+        /*For now we will see if someone above us has the data by
+          doing a functional access on reads.  Fix this later */
+            PacketPtr tmp = new Packet(pkt->req, Packet::ReadReq, -1);
+            tmp->allocate();
+            cache->cpuSidePort->sendFunctional(tmp);
+            bool hit = (tmp->result == Packet::Success);
+            if (hit) {
+                memcpy(pkt->getPtr<uint8_t>(), tmp->getPtr<uint8_t>(),
+                       pkt->getSize());
+                DPRINTF(Cache, "Uni-coherence snoops a read that hit in L1\n");
+            }
+            delete tmp;
+            return hit;
     }
+    return false;
 }
diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh
index 44c752088..9a4aacdec 100644
--- a/src/mem/cache/coherence/uni_coherence.hh
+++ b/src/mem/cache/coherence/uni_coherence.hh
@@ -140,7 +140,7 @@ class UniCoherence
 
     bool hasProtocol() { return false; }
 
-    void propogateInvalidate(PacketPtr pkt, bool isTiming);
+    bool propogateInvalidate(PacketPtr pkt, bool isTiming);
 };
 
 #endif //__UNI_COHERENCE_HH__