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author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-15 03:40:04 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-15 03:40:04 -0500 |
commit | 407233f5d80d04e27234eb70750a7f6ee13acd4f (patch) | |
tree | f13f8e9c0077e478822b17147b2ce8cd4c14cfb0 /src/mem | |
parent | b181cea3645929d11b21a29ac8c3e3ed3079e91b (diff) | |
download | gem5-407233f5d80d04e27234eb70750a7f6ee13acd4f.tar.xz |
mem: Avoid using invalid iterator in cache lock list traversal
Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/cache/blk.hh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh index 6682dd4bb..39d45d6e1 100644 --- a/src/mem/cache/blk.hh +++ b/src/mem/cache/blk.hh @@ -347,15 +347,16 @@ class CacheBlk bool success = false; auto l = lockList.begin(); - while (l != lockList.end() && !success) { + while (!success && l != lockList.end()) { if (l->matches(pkt->req)) { // it's a store conditional, and as far as the // memory system can tell, the requesting // context's lock is still valid. success = true; lockList.erase(l); + } else { + ++l; } - ++l; } req->setExtraData(success ? 1 : 0); |