diff options
author | Nathan Binkert <nate@binkert.org> | 2009-05-26 09:23:13 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2009-05-26 09:23:13 -0700 |
commit | 47877cf2dbd6ee2f1cf9b2c609d37b0589e876ca (patch) | |
tree | 6beb00dfe7e31b9bf82f7aba4710b0c487b6543f /src/mem | |
parent | d93392df28fc6c9a5c70fb6252a12afdc72d9344 (diff) | |
download | gem5-47877cf2dbd6ee2f1cf9b2c609d37b0589e876ca.tar.xz |
types: add a type for thread IDs and try to use it everywhere
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/cache/mshr.cc | 2 | ||||
-rw-r--r-- | src/mem/cache/mshr.hh | 2 | ||||
-rw-r--r-- | src/mem/request.hh | 6 | ||||
-rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 6 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc index 726253c62..100e6126a 100644 --- a/src/mem/cache/mshr.cc +++ b/src/mem/cache/mshr.cc @@ -51,7 +51,7 @@ MSHR::MSHR() { inService = false; ntargets = 0; - threadNum = -1; + threadNum = InvalidThreadID; targets = new TargetList(); deferredTargets = new TargetList(); } diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh index bed7012b0..13395d314 100644 --- a/src/mem/cache/mshr.hh +++ b/src/mem/cache/mshr.hh @@ -138,7 +138,7 @@ class MSHR : public Packet::SenderState, public Printable bool pendingShared; /** Thread number of the miss. */ - short threadNum; + ThreadID threadNum; /** The number of currently allocated targets. */ short ntargets; diff --git a/src/mem/request.hh b/src/mem/request.hh index 3915fa683..901a24f47 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -189,7 +189,7 @@ class Request : public FastAlloc } Request(int asid, Addr vaddr, int size, Flags flags, Addr pc, - int cid, int tid) + int cid, ThreadID tid) { setVirt(asid, vaddr, size, flags, pc); setThreadContext(cid, tid); @@ -201,10 +201,10 @@ class Request : public FastAlloc * Set up CPU and thread numbers. */ void - setThreadContext(int context_id, int thread_id) + setThreadContext(int context_id, ThreadID tid) { _contextId = context_id; - _threadId = thread_id; + _threadId = tid; privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID); } diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index a8306c06f..6908b9168 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -200,9 +200,9 @@ CacheMemory<ENTRY>::CacheMemory(AbstractChip* chip_ptr, int numSetBits, // cout << "Before setting trans address list size" << endl; //create a trans address for each SMT thread // m_trans_address_list.setSize(numThreads); -// for(int i=0; i < numThreads; ++i){ -// cout << "Setting list size for list " << i << endl; -// m_trans_address_list[i].setSize(30); +// for(ThreadID tid = 0; tid < numThreads; ++tid){ +// cout << "Setting list size for list " << tid << endl; +// m_trans_address_list[tid].setSize(30); // } //cout << "CacheMemory constructor finished" << endl; } |