summaryrefslogtreecommitdiff
path: root/src/mem
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2007-03-02 22:34:51 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-02 22:34:51 -0500
commit4e8d2d1593475008b926829e6944a59963166079 (patch)
tree42ff01c4146f48c23179de7d2b01f4e6bdbe97d7 /src/mem
parentd8ada247f4fb107e7dc530ceb96a624d46c8ed9a (diff)
downloadgem5-4e8d2d1593475008b926829e6944a59963166079.tar.xz
make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/packet_access.hh12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index 882aa98d0..552b6dd27 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -53,6 +53,18 @@ Packet::get()
return d;
}
+template<>
+inline Twin32_t
+Packet::get()
+{
+ Twin32_t d;
+ assert(staticData || dynamicData);
+ assert(sizeof(Twin32_t) <= size);
+ d.a = TheISA::gtoh(*(uint32_t*)data);
+ d.b = TheISA::gtoh(*((uint32_t*)data + 1));
+ return d;
+}
+
/** return the value of what is pointed to in the packet. */
template <typename T>