diff options
author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-04 16:27:04 +0100 |
---|---|---|
committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-27 16:00:28 +0000 |
commit | 5187a24d496cd16bfe440f52ff0c45ab0e185306 (patch) | |
tree | c491ebdad23a5f9e57ef62ffeabcf2b87289f5ce /src/mem | |
parent | 685cf2d1f8ae2f2ca3168a650efa1d36120783fe (diff) | |
download | gem5-5187a24d496cd16bfe440f52ff0c45ab0e185306.tar.xz |
sim,cpu,mem,arch: Introduced MasterInfo data structure
With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.
Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/cache/prefetch/base.cc | 2 | ||||
-rw-r--r-- | src/mem/external_master.cc | 2 | ||||
-rw-r--r-- | src/mem/mem_master.hh | 72 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 2 |
4 files changed, 75 insertions, 3 deletions
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index 6b4cf0586..90c6742f9 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -58,7 +58,7 @@ BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p) : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0), system(p->sys), onMiss(p->on_miss), onRead(p->on_read), onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst), - masterId(system->getMasterId(name())), + masterId(system->getMasterId(this)), pageBytes(system->getPageBytes()) { } diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc index e0e8c1e87..373aa84fe 100644 --- a/src/mem/external_master.cc +++ b/src/mem/external_master.cc @@ -57,7 +57,7 @@ ExternalMaster::ExternalMaster(ExternalMasterParams *params) : portName(params->name + ".port"), portType(params->port_type), portData(params->port_data), - masterId(params->system->getMasterId(params->name)) + masterId(params->system->getMasterId(this)) {} BaseMasterPort & diff --git a/src/mem/mem_master.hh b/src/mem/mem_master.hh new file mode 100644 index 000000000..f19682533 --- /dev/null +++ b/src/mem/mem_master.hh @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2018 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Giacomo Travaglini + */ + +/** + * @file + * MasterInfo declaration. + */ + +#ifndef __MEM_MEM_MASTER_HH__ +#define __MEM_MEM_MASTER_HH__ + +#include "mem/request.hh" +#include "sim/sim_object.hh" + +/** + * The MasterInfo class contains data about a specific master. + */ +struct MasterInfo +{ + MasterInfo(const SimObject* _obj, + std::string master_name, + MasterID master_id) + : obj(_obj), masterName(master_name), masterId(master_id) + {} + + /** SimObject related to the Master */ + const SimObject* obj; + + /** Master Name */ + std::string masterName; + + /** Master ID */ + MasterID masterId; +}; + +#endif // __MEM_MEM_MASTER_HH__ diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index b920ff7b0..de5e81057 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -51,7 +51,7 @@ AbstractController::AbstractController(const Params *p) : MemObject(p), Consumer(this), m_version(p->version), m_clusterID(p->cluster_id), - m_masterId(p->system->getMasterId(name())), m_is_blocking(false), + m_masterId(p->system->getMasterId(this)), m_is_blocking(false), m_number_of_TBEs(p->number_of_TBEs), m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), |