diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-18 13:34:52 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-18 13:34:52 -0400 |
commit | 63c2a782d60dffaf7150ed0799767b215bbce6fb (patch) | |
tree | bf576dc58c45031b5a2592f9574ac400876cd070 /src/mem | |
parent | 9c582c7e144aef0bfc9d14bb4690d56d1688496a (diff) | |
parent | 0e2561710b44f811a5e179935d54ef240013d03e (diff) | |
download | gem5-63c2a782d60dffaf7150ed0799767b215bbce6fb.tar.xz |
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/cache/base_cache.cc | 3 | ||||
-rw-r--r-- | src/mem/cache/base_cache.hh | 1 | ||||
-rw-r--r-- | src/mem/cache/cache.hh | 41 | ||||
-rw-r--r-- | src/mem/cache/cache_builder.cc | 4 | ||||
-rw-r--r-- | src/mem/cache/cache_impl.hh | 157 | ||||
-rw-r--r-- | src/mem/cache/miss/mshr_queue.cc | 17 | ||||
-rw-r--r-- | src/mem/cache/tags/fa_lru.hh | 19 | ||||
-rw-r--r-- | src/mem/cache/tags/iic.cc | 102 | ||||
-rw-r--r-- | src/mem/cache/tags/iic.hh | 16 | ||||
-rw-r--r-- | src/mem/cache/tags/lru.cc | 45 | ||||
-rw-r--r-- | src/mem/cache/tags/lru.hh | 16 | ||||
-rw-r--r-- | src/mem/cache/tags/split.cc | 13 | ||||
-rw-r--r-- | src/mem/cache/tags/split.hh | 16 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lifo.cc | 46 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lifo.hh | 16 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lru.cc | 46 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lru.hh | 16 | ||||
-rw-r--r-- | src/mem/page_table.cc | 37 | ||||
-rw-r--r-- | src/mem/page_table.hh | 2 |
19 files changed, 122 insertions, 491 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index ebcf83b92..936a9c1fa 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -34,9 +34,10 @@ */ #include "mem/cache/base_cache.hh" +#include "mem/cache/miss/mshr.hh" +#include "mem/packet_impl.hh" #include "cpu/smt.hh" #include "cpu/base.hh" -#include "mem/cache/miss/mshr.hh" using namespace std; diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 8814abb38..93830b04f 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -58,7 +58,6 @@ enum BlockedCause{ Blocked_NoTargets, Blocked_NoWBBuffers, Blocked_Coherence, - Blocked_Copy, NUM_BLOCKED_CAUSES }; diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 7024ce58a..07d9d6336 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -75,12 +75,6 @@ class Cache : public BaseCache /** Prefetcher */ Prefetcher<TagStore, Buffering> *prefetcher; - /** Do fast copies in this cache. */ - bool doCopy; - - /** Block on a delayed copy. */ - bool blockOnCopy; - /** * The clock ratio of the outgoing bus. * Used for calculating critical word first. @@ -105,18 +99,6 @@ class Cache : public BaseCache Packet * invalidatePkt; Request *invalidateReq; - /** - * Temporarily move a block into a MSHR. - * @todo Remove this when LSQ/SB are fixed and implemented in memtest. - */ - void pseudoFill(Addr addr); - - /** - * Temporarily move a block into an existing MSHR. - * @todo Remove this when LSQ/SB are fixed and implemented in memtest. - */ - void pseudoFill(MSHR *mshr); - public: class Params @@ -125,19 +107,17 @@ class Cache : public BaseCache TagStore *tags; Buffering *missQueue; Coherence *coherence; - bool doCopy; - bool blockOnCopy; BaseCache::Params baseParams; Prefetcher<TagStore, Buffering> *prefetcher; bool prefetchAccess; int hitLatency; Params(TagStore *_tags, Buffering *mq, Coherence *coh, - bool do_copy, BaseCache::Params params, + BaseCache::Params params, Prefetcher<TagStore, Buffering> *_prefetcher, bool prefetch_access, int hit_latency) - : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy), - blockOnCopy(false), baseParams(params), + : tags(_tags), missQueue(mq), coherence(coh), + baseParams(params), prefetcher(_prefetcher), prefetchAccess(prefetch_access), hitLatency(hit_latency) { @@ -192,21 +172,6 @@ class Cache : public BaseCache void handleResponse(Packet * &pkt); /** - * Start handling a copy transaction. - * @param pkt The copy request to perform. - */ - void startCopy(Packet * &pkt); - - /** - * Handle a delayed copy transaction. - * @param pkt The delayed copy request to continue. - * @param addr The address being responded to. - * @param blk The block of the current response. - * @param mshr The mshr being handled. - */ - void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr); - - /** * Selects a coherence message to forward to lower levels of the hierarchy. * @return The coherence message to forward. */ diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index 05a149a1c..03646ec2a 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -113,7 +113,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache) Param<bool> prioritizeRequests; // SimObjectParam<Bus *> in_bus; // SimObjectParam<Bus *> out_bus; - Param<bool> do_copy; SimObjectParam<CoherenceProtocol *> protocol; Param<Addr> trace_addr; Param<int> hash_delay; @@ -163,7 +162,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache) /* INIT_PARAM_DFLT(in_bus, "incoming bus object", NULL), INIT_PARAM(out_bus, "outgoing bus object"), */ - INIT_PARAM_DFLT(do_copy, "perform fast copies in the cache", false), INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL), INIT_PARAM_DFLT(trace_addr, "address to trace", 0), @@ -228,7 +226,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) BUILD_NULL_PREFETCHER(t, comp, b); \ } \ Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \ - do_copy, base_params, \ + base_params, \ /*in_bus, out_bus,*/ pf, \ prefetch_access, hit_latency); \ Cache<CacheTags<t, comp>, b, c> *retval = \ diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 44d7b4895..520e5abb5 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -148,7 +148,6 @@ Cache(const std::string &_name, prefetchAccess(params.prefetchAccess), tags(params.tags), missQueue(params.missQueue), coherence(params.coherence), prefetcher(params.prefetcher), - doCopy(params.doCopy), blockOnCopy(params.blockOnCopy), hitLatency(params.hitLatency) { tags->setCache(this); @@ -198,7 +197,8 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt) /** @todo make the fast write alloc (wh64) work with coherence. */ /** @todo Do we want to do fast writes for writebacks as well? */ if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() && - (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) { + (pkt->cmd == Packet::WriteReq + || pkt->cmd == Packet::WriteInvalidateReq) ) { // not outstanding misses, can do this MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr()); if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) { @@ -255,7 +255,8 @@ Cache<TagStore,Buffering,Coherence>::getPacket() Packet * pkt = missQueue->getPacket(); if (pkt) { if (!pkt->req->isUncacheable()) { - if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++; + if (pkt->cmd == Packet::HardPFReq) + misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++; BlkType *blk = tags->findBlock(pkt); Packet::Command cmd = coherence->getBusCmd(pkt->cmd, (blk)? blk->status : 0); @@ -270,10 +271,12 @@ Cache<TagStore,Buffering,Coherence>::getPacket() template<class TagStore, class Buffering, class Coherence> void -Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success) +Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, + bool success) { if (success && !(pkt && (pkt->flags & NACKED_LINE))) { - if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq) + if (!mshr->pkt->needsResponse() + && !(mshr->pkt->cmd == Packet::UpgradeReq) && (pkt && (pkt->flags & SATISFIED))) { //Writeback, clean up the non copy version of the packet delete pkt; @@ -287,8 +290,10 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool CacheBlk::State old_state = (blk) ? blk->status : 0; CacheBlk::State new_state = coherence->getNewState(pkt,old_state); if (old_state != new_state) - DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n", - pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state); + DPRINTF(Cache, "Block for blk addr %x moving from " + "state %i to %i\n", + pkt->getAddr() & (((ULL(1))<<48)-1), + old_state, new_state); //Set the state on the upgrade memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); PacketList writebacks; @@ -320,7 +325,8 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt) ((MSHR*)pkt->senderState)->pkt = pkt; if (pkt->result == Packet::Nacked) { //pkt->reinitFromRequest(); - warn("NACKs from devices not connected to the same bus not implemented\n"); + warn("NACKs from devices not connected to the same bus " + "not implemented\n"); return; } if (pkt->result == Packet::BadAddress) { @@ -336,8 +342,10 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt) PacketList writebacks; CacheBlk::State new_state = coherence->getNewState(pkt,old_state); if (old_state != new_state) - DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n", - pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state); + DPRINTF(Cache, "Block for blk addr %x moving from " + "state %i to %i\n", + pkt->getAddr() & (((ULL(1))<<48)-1), + old_state, new_state); blk = tags->handleFill(blk, (MSHR*)pkt->senderState, new_state, writebacks, pkt); while (!writebacks.empty()) { @@ -350,43 +358,6 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt) } template<class TagStore, class Buffering, class Coherence> -void -Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr) -{ - // Need to temporarily move this blk into MSHRs - MSHR *mshr = missQueue->allocateTargetList(addr); - int lat; - PacketList dummy; - // Read the data into the mshr - BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false); - assert(dummy.empty()); - assert(mshr->pkt->flags & SATISFIED); - // can overload order since it isn't used on non pending blocks - mshr->order = blk->status; - // temporarily remove the block from the cache. - tags->invalidateBlk(addr); -} - -template<class TagStore, class Buffering, class Coherence> -void -Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr) -{ - // Need to temporarily move this blk into MSHRs - assert(mshr->pkt->cmd == Packet::ReadReq); - int lat; - PacketList dummy; - // Read the data into the mshr - BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false); - assert(dummy.empty()); - assert(mshr->pkt->flags & SATISFIED); - // can overload order since it isn't used on non pending blocks - mshr->order = blk->status; - // temporarily remove the block from the cache. - tags->invalidateBlk(mshr->pkt->getAddr()); -} - - -template<class TagStore, class Buffering, class Coherence> Packet * Cache<TagStore,Buffering,Coherence>::getCoherencePacket() { @@ -416,30 +387,36 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) BlkType *blk = tags->findBlock(pkt); MSHR *mshr = missQueue->findMSHR(blk_addr); if (coherence->hasProtocol()) { //@todo Move this into handle bus req - //If we find an mshr, and it is in service, we need to NACK or invalidate + //If we find an mshr, and it is in service, we need to NACK or + //invalidate if (mshr) { if (mshr->inService) { if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill()) - && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) { - //If the outstanding request was an invalidate (upgrade,readex,..) - //Then we need to ACK the request until we get the data - //Also NACK if the outstanding request is not a cachefill (writeback) + && (pkt->cmd != Packet::InvalidateReq + && pkt->cmd != Packet::WriteInvalidateReq)) { + //If the outstanding request was an invalidate + //(upgrade,readex,..) Then we need to ACK the request + //until we get the data Also NACK if the outstanding + //request is not a cachefill (writeback) assert(!(pkt->flags & SATISFIED)); pkt->flags |= SATISFIED; pkt->flags |= NACKED_LINE; ///@todo NACK's from other levels - //warn("NACKs from devices not connected to the same bus not implemented\n"); + //warn("NACKs from devices not connected to the same bus " + //"not implemented\n"); //respondToSnoop(pkt, curTick + hitLatency); return; } else { - //The supplier will be someone else, because we are waiting for - //the data. This should cause this cache to be forced to go to - //the shared state, not the exclusive even though the shared line - //won't be asserted. But for now we will just invlidate ourselves - //and allow the other cache to go into the exclusive state. - //@todo Make it so a read to a pending read doesn't invalidate. - //@todo Make it so that a read to a pending read can't be exclusive now. + //The supplier will be someone else, because we are + //waiting for the data. This should cause this cache to + //be forced to go to the shared state, not the exclusive + //even though the shared line won't be asserted. But for + //now we will just invlidate ourselves and allow the other + //cache to go into the exclusive state. @todo Make it so + //a read to a pending read doesn't invalidate. @todo Make + //it so that a read to a pending read can't be exclusive + //now. //Set the address so find match works //panic("Don't have invalidates yet\n"); @@ -447,7 +424,8 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) //Append the invalidate on missQueue->addTarget(mshr,invalidatePkt); - DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1)); + DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", + pkt->getAddr() & (((ULL(1))<<48)-1)); return; } } @@ -455,7 +433,8 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) //We also need to check the writeback buffers and handle those std::vector<MSHR *> writebacks; if (missQueue->findWrites(blk_addr, writebacks)) { - DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1)); + DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", + pkt->getAddr() & (((ULL(1))<<48)-1)); //Look through writebacks for any non-uncachable writes, use that for (int i=0; i<writebacks.size(); i++) { @@ -483,7 +462,8 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) } if (pkt->isInvalidate()) { - //This must be an upgrade or other cache will take ownership + //This must be an upgrade or other cache will take + //ownership missQueue->markInService(mshr->pkt, mshr); } return; @@ -494,16 +474,17 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) CacheBlk::State new_state; bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); if (satisfy) { - DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data," - "new state is %i\n", + DPRINTF(Cache, "Cache snooped a %s request for addr %x and " + "now supplying data, new state is %i\n", pkt->cmdString(), blk_addr, new_state); tags->handleSnoop(blk, new_state, pkt); respondToSnoop(pkt, curTick + hitLatency); return; } - if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n", - pkt->cmdString(), blk_addr, new_state); + if (blk) + DPRINTF(Cache, "Cache snooped a %s request for addr %x, " + "new state is %i\n", pkt->cmdString(), blk_addr, new_state); tags->handleSnoop(blk, new_state); } @@ -516,12 +497,13 @@ Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt) //Need to mark it as not in service, and retry for bus assert(0); //Yeah, we saw a NACK come through - //For now this should never get called, we return false when we see a NACK - //instead, by doing this we allow the bus_blocked mechanism to handle the retry - //For now it retrys in just 2 cycles, need to figure out how to change that - //Eventually we will want to also have success come in as a parameter - //Need to make sure that we handle the functionality that happens on successufl - //return of the sendAddr function + //For now this should never get called, we return false when we see a + //NACK instead, by doing this we allow the bus_blocked mechanism to + //handle the retry For now it retrys in just 2 cycles, need to figure + //out how to change that Eventually we will want to also have success + //come in as a parameter Need to make sure that we handle the + //functionality that happens on successufl return of the sendAddr + //function } } @@ -538,7 +520,8 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr) */ template<class TagStore, class Buffering, class Coherence> Tick -Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort) +Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, + CachePort* otherSidePort) { // MemDebug::cacheProbe(pkt); if (!pkt->req->isUncacheable()) { @@ -687,13 +670,17 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; CacheBlk::State old_state = (blk) ? blk->status : 0; - CacheBlk::State new_state = coherence->getNewState(busPkt, old_state); - DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n", - busPkt->cmdString(), - busPkt->getAddr() & (((ULL(1))<<48)-1), old_state); + CacheBlk::State new_state = + coherence->getNewState(busPkt, old_state); + DPRINTF(Cache, + "Receive response:%s for blk addr %x in state %i\n", + busPkt->cmdString(), + busPkt->getAddr() & (((ULL(1))<<48)-1), old_state); if (old_state != new_state) - DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n", - busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state); + DPRINTF(Cache, "Block for blk addr %x moving from " + "state %i to %i\n", + busPkt->getAddr() & (((ULL(1))<<48)-1), + old_state, new_state); tags->handleFill(blk, busPkt, new_state, @@ -743,15 +730,17 @@ Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt) CacheBlk::State new_state = 0; bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); if (satisfy) { - DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data," - "new state is %i\n", + DPRINTF(Cache, "Cache snooped a %s request for addr %x and " + "now supplying data, new state is %i\n", pkt->cmdString(), blk_addr, new_state); tags->handleSnoop(blk, new_state, pkt); return hitLatency; } - if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n", - pkt->cmdString(), blk_addr, new_state); + if (blk) + DPRINTF(Cache, "Cache snooped a %s request for addr %x, " + "new state is %i\n", + pkt->cmdString(), blk_addr, new_state); tags->handleSnoop(blk, new_state); return 0; } diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index 9d2a692cf..777443e5f 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -103,23 +103,6 @@ MSHRQueue::findPending(Packet * &pkt) const return mshr; } } - - //need to check destination address for copies. - //TEMP NOT DOING COPIES -#if 0 - if (mshr->pkt->cmd == Copy) { - Addr dest = mshr->pkt->dest; - if (dest < pkt->addr) { - if (dest + mshr->pkt->size > pkt->addr) { - return mshr; - } - } else { - if (pkt->addr + pkt->size > dest) { - return mshr; - } - } - } -#endif } return NULL; } diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index f9d4d7109..0fc54902b 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -322,25 +322,6 @@ public: PacketList &writebacks) { } - - /** - * Unimplemented. Perform a cache block copy from block aligned addresses. - * @param source The block aligned source address. - * @param dest The block aligned destination adddress. - * @param asid The address space ID. - * @param writebacks List for any generated writeback pktuests. - */ - void doCopy(Addr source, Addr dest, PacketList &writebacks) - { - } - - /** - * Unimplemented. - */ - void fixCopy(Packet * &pkt, PacketList &writebacks) - { - } - }; #endif diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index 1377c8613..bf1d9ece4 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -711,8 +711,8 @@ IIC::invalidateBlk(Addr addr) } void -IIC::readData(IICTag *blk, uint8_t *data){ -// assert(cache->doData()); +IIC::readData(IICTag *blk, uint8_t *data) +{ assert(blk->size <= trivialSize || blk->numData > 0); int data_size = blk->size; if (data_size > trivialSize) { @@ -729,8 +729,8 @@ IIC::readData(IICTag *blk, uint8_t *data){ void IIC::writeData(IICTag *blk, uint8_t *write_data, int size, - PacketList & writebacks){ -// assert(cache->doData()); + PacketList & writebacks) +{ assert(size < blkSize || !blk->isCompressed()); DPRINTF(IIC, "Writing %d bytes to %x\n", size, blk->tag<<tagShift); @@ -750,10 +750,6 @@ IIC::writeData(IICTag *blk, uint8_t *write_data, int size, // can free data blocks for (int i=num_subs; i < blk->numData; ++i){ // decrement reference count and compare to zero - /** - * @todo - * Make this work with copying. - */ if (--dataReferenceCount[blk->data_ptr[i]] == 0) { freeDataBlock(blk->data_ptr[i]); } @@ -775,96 +771,6 @@ IIC::writeData(IICTag *blk, uint8_t *write_data, int size, } -/** - * @todo This code can break if the src is evicted to get a tag for the dest. - */ -void -IIC::doCopy(Addr source, Addr dest, PacketList &writebacks) -{ -//Copy unsuported now -#if 0 - IICTag *dest_tag = findBlock(dest); - - if (dest_tag) { - for (int i = 0; i < dest_tag->numData; ++i) { - if (--dataReferenceCount[dest_tag->data_ptr[i]] == 0) { - freeDataBlock(dest_tag->data_ptr[i]); - } - } - // Reset replacement entry - } else { - dest_tag = getFreeTag(hash(dest), writebacks); - dest_tag->re = (void*) repl->add(dest_tag - tagStore); - dest_tag->set = hash(dest); - dest_tag->tag = extractTag(dest); - dest_tag->status = BlkValid | BlkWritable; - } - // Find the source tag here since it might move if we need to find a - // tag for the destination. - IICTag *src_tag = findBlock(source); - assert(src_tag); - assert(!cache->doData() || src_tag->size <= trivialSize - || src_tag->numData > 0); - // point dest to source data and inc counter - for (int i = 0; i < src_tag->numData; ++i) { - dest_tag->data_ptr[i] = src_tag->data_ptr[i]; - ++dataReferenceCount[dest_tag->data_ptr[i]]; - } - - // Maintain fast access data. - memcpy(dest_tag->data, src_tag->data, blkSize); - - dest_tag->xc = src_tag->xc; - dest_tag->size = src_tag->size; - dest_tag->numData = src_tag->numData; - if (src_tag->numData == 0) { - // Data is stored in the trivial data, just copy it. - memcpy(dest_tag->trivialData, src_tag->trivialData, src_tag->size); - } - - dest_tag->status |= BlkDirty; - if (dest_tag->size < blkSize) { - dest_tag->status |= BlkCompressed; - } else { - dest_tag->status &= ~BlkCompressed; - } -#endif -} - -void -IIC::fixCopy(Packet * &pkt, PacketList &writebacks) -{ -#if 0 - // if reference counter is greater than 1, do copy - // else do write - Addr blk_addr = blkAlign(pkt->getAddr); - IICTag* blk = findBlock(blk_addr); - - if (blk->numData > 0 && dataReferenceCount[blk->data_ptr[0]] != 1) { - // copy the data - // Mark the block as referenced so it doesn't get replaced. - blk->status |= BlkReferenced; - for (int i = 0; i < blk->numData; ++i){ - unsigned long new_data = getFreeDataBlock(writebacks); - // Need to refresh pointer - /** - * @todo Remove this refetch once we change IIC to pointer based - */ - blk = findBlock(blk_addr); - assert(blk); - if (cache->doData()) { - memcpy(&(dataBlks[new_data][0]), - &(dataBlks[blk->data_ptr[i]][0]), - subSize); - } - dataReferenceCount[blk->data_ptr[i]]--; - dataReferenceCount[new_data]++; - blk->data_ptr[i] = new_data; - } - } -#endif -} - void IIC::cleanupRefs() { diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 2357bdce3..905d480c5 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -498,22 +498,6 @@ class IIC : public BaseTags PacketList & writebacks); /** - * Perform a block aligned copy from the source address to the destination. - * @param source The block-aligned source address. - * @param dest The block-aligned destination address. - * @param asid The address space DI. - * @param writebacks List for any generated writeback pktuests. - */ - void doCopy(Addr source, Addr dest, PacketList &writebacks); - - /** - * If a block is currently marked copy on write, copy it before writing. - * @param pkt The write request. - * @param writebacks List for any generated writeback pktuests. - */ - void fixCopy(Packet * &pkt, PacketList &writebacks); - - /** * Called at end of simulation to complete average block reference stats. */ virtual void cleanupRefs(); diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 976bbeff2..a9ae049c3 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -251,51 +251,6 @@ LRU::invalidateBlk(Addr addr) } void -LRU::doCopy(Addr source, Addr dest, PacketList &writebacks) -{ - assert(source == blkAlign(source)); - assert(dest == blkAlign(dest)); - LRUBlk *source_blk = findBlock(source); - assert(source_blk); - LRUBlk *dest_blk = findBlock(dest); - if (dest_blk == NULL) { - // Need to do a replacement - Request *search = new Request(dest,1,0); - Packet * pkt = new Packet(search, Packet::ReadReq, -1); - BlkList dummy_list; - dest_blk = findReplacement(pkt, writebacks, dummy_list); - if (dest_blk->isValid() && dest_blk->isModified()) { - // Need to writeback data. -/* pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag, - dest_blk->set), - dest_blk->req->asid, - dest_blk->xc, - blkSize, - dest_blk->data, - dest_blk->size); -*/ - Request *writebackReq = new Request(regenerateBlkAddr(dest_blk->tag, - dest_blk->set), - blkSize, 0); - Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1); - writeback->allocate(); - memcpy(writeback->getPtr<uint8_t>(),dest_blk->data, blkSize); - writebacks.push_back(writeback); - } - dest_blk->tag = extractTag(dest); - delete search; - delete pkt; - } - /** - * @todo Can't assume the status once we have coherence on copies. - */ - - // Set this block as readable, writeable, and dirty. - dest_blk->status = 7; - memcpy(dest_blk->data, source_blk->data, blkSize); -} - -void LRU::cleanupRefs() { for (int i = 0; i < numSets*assoc; ++i) { diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh index a3a56a0e6..9f0a05ee8 100644 --- a/src/mem/cache/tags/lru.hh +++ b/src/mem/cache/tags/lru.hh @@ -303,22 +303,6 @@ public: } /** - * Perform a block aligned copy from the source address to the destination. - * @param source The block-aligned source address. - * @param dest The block-aligned destination address. - * @param asid The address space DI. - * @param writebacks List for any generated writeback pktuests. - */ - void doCopy(Addr source, Addr dest, PacketList &writebacks); - - /** - * No impl. - */ - void fixCopy(Packet * &pkt, PacketList &writebacks) - { - } - - /** * Called at end of simulation to complete average block reference stats. */ virtual void cleanupRefs(); diff --git a/src/mem/cache/tags/split.cc b/src/mem/cache/tags/split.cc index 690eea22e..cad18e885 100644 --- a/src/mem/cache/tags/split.cc +++ b/src/mem/cache/tags/split.cc @@ -422,19 +422,6 @@ Split::invalidateBlk(Addr addr) } void -Split::doCopy(Addr source, Addr dest, PacketList &writebacks) -{ - if (lru->probe( source)) - lru->doCopy(source, dest, writebacks); - else { - if (lifo && lifo_net) - lifo_net->doCopy(source, dest, writebacks); - else if (lru_net) - lru_net->doCopy(source, dest, writebacks); - } -} - -void Split::cleanupRefs() { lru->cleanupRefs(); diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh index f0091e971..708058e96 100644 --- a/src/mem/cache/tags/split.hh +++ b/src/mem/cache/tags/split.hh @@ -311,22 +311,6 @@ class Split : public BaseTags } /** - * Perform a block aligned copy from the source address to the destination. - * @param source The block-aligned source address. - * @param dest The block-aligned destination address. - * @param asid The address space DI. - * @param writebacks List for any generated writeback pktuests. - */ - void doCopy(Addr source, Addr dest, PacketList &writebacks); - - /** - * No impl. - */ - void fixCopy(Packet * &pkt, PacketList &writebacks) - { - } - - /** * Called at end of simulation to complete average block reference stats. */ virtual void cleanupRefs(); diff --git a/src/mem/cache/tags/split_lifo.cc b/src/mem/cache/tags/split_lifo.cc index 6fcbf3597..4e9375070 100644 --- a/src/mem/cache/tags/split_lifo.cc +++ b/src/mem/cache/tags/split_lifo.cc @@ -347,52 +347,6 @@ SplitLIFO::invalidateBlk(Addr addr) } void -SplitLIFO::doCopy(Addr source, Addr dest, PacketList &writebacks) -{ -//Copy Unsuported for now -#if 0 - assert(source == blkAlign(source)); - assert(dest == blkAlign(dest)); - SplitBlk *source_blk = findBlock(source); - assert(source_blk); - SplitBlk *dest_blk = findBlock(dest); - if (dest_blk == NULL) { - // Need to do a replacement - Packet * pkt = new Packet(); - pkt->paddr = dest; - BlkList dummy_list; - dest_blk = findReplacement(pkt, writebacks, dummy_list); - if (dest_blk->isValid() && dest_blk->isModified()) { - // Need to writeback data. - pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag, - dest_blk->set), - dest_blk->xc, - blkSize, - (cache->doData())?dest_blk->data:0, - dest_blk->size); - writebacks.push_back(pkt); - } - dest_blk->tag = extractTag(dest); - /** - * @todo Do we need to pass in the execution context, or can we - * assume its the same? - */ - assert(source_blk->xc); - dest_blk->xc = source_blk->xc; - } - /** - * @todo Can't assume the status once we have coherence on copies. - */ - - // Set this block as readable, writeable, and dirty. - dest_blk->status = 7; - if (cache->doData()) { - memcpy(dest_blk->data, source_blk->data, blkSize); - } -#endif -} - -void SplitLIFO::cleanupRefs() { for (int i = 0; i < numBlks; ++i) { diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh index 355a66162..ddc7fdeec 100644 --- a/src/mem/cache/tags/split_lifo.hh +++ b/src/mem/cache/tags/split_lifo.hh @@ -326,22 +326,6 @@ public: } /** - * Perform a block aligned copy from the source address to the destination. - * @param source The block-aligned source address. - * @param dest The block-aligned destination address. - * @param asid The address space DI. - * @param writebacks List for any generated writeback pktuests. - */ - void doCopy(Addr source, Addr dest, PacketList &writebacks); - - /** - * No impl. - */ - void fixCopy(Packet * &pkt, PacketList &writebacks) - { - } - - /** * Called at end of simulation to complete average block reference stats. */ virtual void cleanupRefs(); diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc index 4381923bd..4aba1c37f 100644 --- a/src/mem/cache/tags/split_lru.cc +++ b/src/mem/cache/tags/split_lru.cc @@ -272,52 +272,6 @@ SplitLRU::invalidateBlk(Addr addr) } void -SplitLRU::doCopy(Addr source, Addr dest, PacketList &writebacks) -{ -//Copy not supported for now -#if 0 - assert(source == blkAlign(source)); - assert(dest == blkAlign(dest)); - SplitBlk *source_blk = findBlock(source); - assert(source_blk); - SplitBlk *dest_blk = findBlock(dest); - if (dest_blk == NULL) { - // Need to do a replacement - Packet * pkt = new Packet(); - pkt->paddr = dest; - BlkList dummy_list; - dest_blk = findReplacement(pkt, writebacks, dummy_list); - if (dest_blk->isValid() && dest_blk->isModified()) { - // Need to writeback data. - pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag, - dest_blk->set), - dest_blk->xc, - blkSize, - (cache->doData())?dest_blk->data:0, - dest_blk->size); - writebacks.push_back(pkt); - } - dest_blk->tag = extractTag(dest); - /** - * @todo Do we need to pass in the execution context, or can we - * assume its the same? - */ - assert(source_blk->xc); - dest_blk->xc = source_blk->xc; - } - /** - * @todo Can't assume the status once we have coherence on copies. - */ - - // Set this block as readable, writeable, and dirty. - dest_blk->status = 7; - if (cache->doData()) { - memcpy(dest_blk->data, source_blk->data, blkSize); - } -#endif -} - -void SplitLRU::cleanupRefs() { for (int i = 0; i < numSets*assoc; ++i) { diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh index 72aebac9c..71f921177 100644 --- a/src/mem/cache/tags/split_lru.hh +++ b/src/mem/cache/tags/split_lru.hh @@ -309,22 +309,6 @@ public: } /** - * Perform a block aligned copy from the source address to the destination. - * @param source The block-aligned source address. - * @param dest The block-aligned destination address. - * @param asid The address space DI. - * @param writebacks List for any generated writeback pktuests. - */ - void doCopy(Addr source, Addr dest, PacketList &writebacks); - - /** - * No impl. - */ - void fixCopy(Packet * &pkt, PacketList &writebacks) - { - } - - /** * Called at end of simulation to complete average block reference stats. */ virtual void cleanupRefs(); diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index 2b460306f..32da4282c 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -27,6 +27,7 @@ * * Authors: Steve Reinhardt * Ron Dreslinski + * Ali Saidi */ /** @@ -97,6 +98,8 @@ PageTable::allocate(Addr vaddr, int64_t size) // starting address must be page aligned assert(pageOffset(vaddr) == 0); + DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); + for (; size > 0; size -= pageSize, vaddr += pageSize) { m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr); @@ -159,3 +162,37 @@ PageTable::translate(RequestPtr &req) req->setPaddr(paddr); return page_check(req->getPaddr(), req->getSize()); } + +void +PageTable::serialize(std::ostream &os) +{ + paramOut(os, "ptable.size", pTable.size()); + int count = 0; + + m5::hash_map<Addr,Addr>::iterator iter; + while (iter != pTable.end()) { + paramOut(os, csprintf("ptable.entry%dvaddr", count),iter->first); + paramOut(os, csprintf("ptable.entry%dpaddr", count),iter->second); + ++count; + } + assert(count == pTable.size()); +} + +void +PageTable::unserialize(Checkpoint *cp, const std::string §ion) +{ + int i = 0, count; + paramIn(cp, section, "ptable.size", count); + Addr vaddr, paddr; + + pTable.clear(); + + while(i < count) { + paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr); + paramIn(cp, section, csprintf("ptable.entry%dpaddr", i), paddr); + pTable[vaddr] = paddr; + ++i; + } + +} + diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index fce063280..0e2b1f58c 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -95,6 +95,8 @@ class PageTable */ Fault translate(RequestPtr &req); + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); }; #endif |