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authorNilay Vaish <nilay@cs.wisc.edu>2012-01-23 11:07:11 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-01-23 11:07:11 -0600
commit9481d05b8aea0faf336f604f3e18b451d5197c12 (patch)
treeb5f2ee3155149449b1b187f0d3d64d511ea113fe /src/mem
parentacd289b7ef5862bdac391672f0e1ad20fbfadab0 (diff)
downloadgem5-9481d05b8aea0faf336f604f3e18b451d5197c12.tar.xz
MemCmd: Add a command for invalidation requests to LSQ
This command will be sent from the memory system (Ruby) to the LSQ of an O3 CPU so that the LSQ, if it needs to, invalidates the address in the request packet.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/packet.cc3
-rw-r--r--src/mem/packet.hh1
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 64f4fcd14..4c3a785dc 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -168,6 +168,9 @@ MemCmd::commandInfo[] =
{ SET2(IsRequest, IsPrint), InvalidCmd, "PrintReq" },
/* Flush Request */
{ SET3(IsRequest, IsFlush, NeedsExclusive), InvalidCmd, "FlushReq" },
+ /* Invalidation Request */
+ { SET3(NeedsExclusive, IsInvalidate, IsRequest),
+ InvalidCmd, "InvalidationReq" },
};
bool
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 6347c21ea..e49ce7577 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -108,6 +108,7 @@ class MemCmd
// Fake simulator-only commands
PrintReq, // Print state matching address
FlushReq, //request for a cache flush
+ InvalidationReq, // request for address to be invalidated from lsq
NUM_MEM_CMDS
};