diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-03-21 21:22:20 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-03-21 21:22:20 -0700 |
commit | c48a7353362a1978ef83652a6679613d9c11bdc6 (patch) | |
tree | 5aa116b33ba20c78c04456ae73f74b9348485428 /src/mem | |
parent | 1765badda28edcf95bed8f1b3a2ca7270cb830e3 (diff) | |
download | gem5-c48a7353362a1978ef83652a6679613d9c11bdc6.tar.xz |
ruby: Fix MOESI_hammer cache profiler calls for L2 misses
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 4bdfcb23d..10a14e2e7 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -683,7 +683,8 @@ machine(L1Cache, "AMD Hammer-like protocol") L1IcacheMemory.profileMiss(in_msg); } else if (L1DcacheMemory.isTagPresent(address)) { L1DcacheMemory.profileMiss(in_msg); - } else { + } + if (L2cacheMemory.isTagPresent(address) == false) { L2cacheMemory.profileMiss(in_msg); } } @@ -724,12 +725,14 @@ machine(L1Cache, "AMD Hammer-like protocol") transition({I, S, O, M, MM}, L2_to_L1D) { ii_allocateL1DCacheBlock; tt_copyFromL2toL1; // Not really needed for state I + uu_profileMiss; rr_deallocateL2CacheBlock; } transition({I, S, O, M, MM}, L2_to_L1I) { jj_allocateL1ICacheBlock; tt_copyFromL2toL1; // Not really needed for state I + uu_profileMiss; rr_deallocateL2CacheBlock; } |