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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:20 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:20 -0800 |
| commit | f6b828d068b046df17b462a4d05af957c038a3a8 (patch) | |
| tree | 1f7be86e41467862c9377e3ca78fa661cc270aed /src/mem | |
| parent | 2d91e741e8ffc8ae3d40f1e849db87e69af7bfa9 (diff) | |
| download | gem5-f6b828d068b046df17b462a4d05af957c038a3a8.tar.xz | |
style: eliminate explicit boolean comparisons
Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.
Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/ruby/common/WriteMask.hh | 2 | ||||
| -rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc | 4 | ||||
| -rw-r--r-- | src/mem/ruby/system/GPUCoalescer.cc | 2 | ||||
| -rw-r--r-- | src/mem/slicc/symbols/Transition.py | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/mem/ruby/common/WriteMask.hh b/src/mem/ruby/common/WriteMask.hh index 2de02ef74..0ba69891a 100644 --- a/src/mem/ruby/common/WriteMask.hh +++ b/src/mem/ruby/common/WriteMask.hh @@ -71,7 +71,7 @@ class WriteMask test(int offset) { assert(offset < mSize); - return mMask[offset] == true; + return mMask[offset]; } void diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc index 06afee845..2387d2e8a 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc @@ -188,8 +188,8 @@ SWallocator_d::arbitrate_outports() m_router->curCycle()); // This Input VC should now be empty - assert(m_input_unit[inport]->isReady(invc, - m_router->curCycle()) == false); + assert(!m_input_unit[inport]-> + isReady(invc, m_router->curCycle())); m_input_unit[inport]->set_vc_state(IDLE_, invc, m_router->curCycle()); diff --git a/src/mem/ruby/system/GPUCoalescer.cc b/src/mem/ruby/system/GPUCoalescer.cc index d4629a0b7..69f79187a 100644 --- a/src/mem/ruby/system/GPUCoalescer.cc +++ b/src/mem/ruby/system/GPUCoalescer.cc @@ -320,7 +320,7 @@ GPUCoalescer::insertRequest(PacketPtr pkt, RubyRequestType request_type) assert(m_outstanding_count == total_outstanding); // See if we should schedule a deadlock check - if (deadlockCheckEvent.scheduled() == false) { + if (!deadlockCheckEvent.scheduled()) { schedule(deadlockCheckEvent, m_deadlock_threshold + curTick()); } diff --git a/src/mem/slicc/symbols/Transition.py b/src/mem/slicc/symbols/Transition.py index 8f88352c8..3fd5a4401 100644 --- a/src/mem/slicc/symbols/Transition.py +++ b/src/mem/slicc/symbols/Transition.py @@ -43,7 +43,7 @@ class Transition(Symbol): if func.c_ident == 'getNextState_Addr': found = True break - if found == False: + if not found: fatal("Machine uses a wildcard transition without getNextState defined") self.nextState = WildcardState(machine.symtab, '*', location) |