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authorBrad Beckmann <Brad.Beckmann@amd.com>2015-07-20 09:15:18 -0500
committerBrad Beckmann <Brad.Beckmann@amd.com>2015-07-20 09:15:18 -0500
commit6b52f828cc886cd5d84dfb76a61140869c6add23 (patch)
treefab3ae20b0ab148cc1c472097c7d7b5b48ea5362 /src/mem
parent848861a17d72b5c555b0b36d594cc66ac1de8c12 (diff)
downloadgem5-6b52f828cc886cd5d84dfb76a61140869c6add23.tar.xz
ruby: improved stall and wait debugging
Added dprintfs and asserts for identifying stall and wait bugs.
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/ruby/network/MessageBuffer.cc2
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc7
2 files changed, 7 insertions, 2 deletions
diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc
index d823c0a1f..484d2876b 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -295,7 +295,7 @@ MessageBuffer::reanalyzeList(list<MsgPtr> &lt, Tick schdTick)
void
MessageBuffer::reanalyzeMessages(const Address& addr)
{
- DPRINTF(RubyQueue, "ReanalyzeMessages\n");
+ DPRINTF(RubyQueue, "ReanalyzeMessages %s\n", addr);
assert(m_stall_msg_map.count(addr) > 0);
Tick curTick = m_receiver->clockEdge();
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 1ac99c882..dfcd61ab2 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -26,8 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "mem/protocol/MemoryMsg.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
+
+#include "debug/RubyQueue.hh"
+#include "mem/protocol/MemoryMsg.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"
#include "sim/system.hh"
@@ -103,6 +105,9 @@ AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
msgVec->resize(m_in_ports, NULL);
m_waiting_buffers[addr] = msgVec;
}
+ DPRINTF(RubyQueue, "stalling %s port %d addr %s\n", buf, m_cur_in_port,
+ addr);
+ assert(m_in_ports > m_cur_in_port);
(*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
}