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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
| commit | 90b1775a8f87834d4c27d4c98483bb7b1e5e9679 (patch) | |
| tree | 5c06b3e32bde9938dc977e1a59c288e87075b521 /src/mem | |
| parent | 6bed6e0352a68723ea55017b3e09a8c279af11ec (diff) | |
| download | gem5-90b1775a8f87834d4c27d4c98483bb7b1e5e9679.tar.xz | |
cpu: Add support for instructions that zero cache lines.
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/request.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/request.hh b/src/mem/request.hh index ebf0ebb58..28d378628 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -114,6 +114,11 @@ class Request /** This request is made in privileged mode. */ static const FlagsType PRIVILEGED = 0x00008000; + /** This is a write that is targeted and zeroing an entire cache block. + * There is no need for a read/modify/write + */ + static const FlagsType CACHE_BLOCK_ZERO = 0x00010000; + /** The request should not cause a memory access. */ static const FlagsType NO_ACCESS = 0x00080000; /** This request will lock or unlock the accessed memory. When used with |