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| author | Lisa Hsu <Lisa.Hsu@amd.com> | 2012-04-06 13:47:08 -0700 |
|---|---|---|
| committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2012-04-06 13:47:08 -0700 |
| commit | a5287efc58ed783b6c03d0fcf7e3f3499533206a (patch) | |
| tree | 17c9622badc02d2079bfd5d67046cb6ceef66389 /src/mem | |
| parent | 5dfa4cd3f5f0091ea8edf1e3673743b48836650d (diff) | |
| download | gem5-a5287efc58ed783b6c03d0fcf7e3f3499533206a.tar.xz | |
slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 85df3f9e8..7d863e349 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -499,6 +499,13 @@ $c_ident::$c_ident(const Params *p) code(''' m_${{seq}}_ptr->setController(this); ''') + + else: + for seq in sequencers: + code(''' +m_${{seq}}_ptr->setController(this); + ''') + # # For the DMA controller, pass the sequencer a pointer to the # controller. |