mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

52 files changed, 118 insertions, 111 deletions

diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 5bffc30af..5b4c718c2 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -40,9 +40,9 @@
 #          Andreas Hansson
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class AbstractMemory(MemObject):
+class AbstractMemory(ClockedObject):
     type = 'AbstractMemory'
     abstract = True
     cxx_header = "mem/abstract_mem.hh"
diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index a1ddaeb7a..d2136f504 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Hansson
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
 
 # An address mapper changes the packet addresses in going from the
 # slave port side of the mapper to the master port side. When the
@@ -44,7 +44,7 @@ from m5.objects.MemObject import MemObject
 # necessary range updates. Note that snoop requests that travel from
 # the master port (i.e. the memory side) to the slave port are
 # currently not modified.
-class AddrMapper(MemObject):
+class AddrMapper(SimObject):
     type = 'AddrMapper'
     cxx_header = 'mem/addr_mapper.hh'
     abstract = True
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 34af552e3..9e86c1a41 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -40,9 +40,9 @@
 #          Andreas Hansson
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class Bridge(MemObject):
+class Bridge(ClockedObject):
     type = 'Bridge'
     cxx_header = "mem/bridge.hh"
     slave = SlavePort('Slave port')
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index fc53ef1f0..d63243722 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -38,12 +38,12 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5.objects.MemObject import MemObject
 from m5.objects.System import System
+from m5.SimObject import SimObject
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
-class CommMonitor(MemObject):
+class CommMonitor(SimObject):
     type = 'CommMonitor'
     cxx_header = "mem/comm_monitor.hh"
 
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index 883e27727..5a9a5bf9d 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -39,9 +39,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
 
-class ExternalMaster(MemObject):
+class ExternalMaster(SimObject):
     type = 'ExternalMaster'
     cxx_header = "mem/external_master.hh"
 
diff --git a/src/mem/ExternalSlave.py b/src/mem/ExternalSlave.py
index 7be5fd8a9..c5fd628f7 100644
--- a/src/mem/ExternalSlave.py
+++ b/src/mem/ExternalSlave.py
@@ -36,9 +36,9 @@
 # Authors: Andrew Bardsley
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
 
-class ExternalSlave(MemObject):
+class ExternalSlave(SimObject):
     type = 'ExternalSlave'
     cxx_header = "mem/external_slave.hh"
 
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 7460cd13b..4a7adc8fe 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -35,7 +35,6 @@
 #
 # Authors: Marco Elver
 
-from m5.objects.MemObject import MemObject
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
@@ -44,7 +43,7 @@ class MemChecker(SimObject):
     type = 'MemChecker'
     cxx_header = "mem/mem_checker.hh"
 
-class MemCheckerMonitor(MemObject):
+class MemCheckerMonitor(SimObject):
     type = 'MemCheckerMonitor'
     cxx_header = "mem/mem_checker_monitor.hh"
 
diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index 415cef4ce..2dedf3267 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -36,9 +36,9 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class MemDelay(MemObject):
+class MemDelay(ClockedObject):
     type = 'MemDelay'
     cxx_header = 'mem/mem_delay.hh'
     abstract = True
diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index 02dcd4c7e..3331aeea6 100644
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -42,12 +42,12 @@
 #          Erfan Azarkhish
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
 # SerialLink is a simple variation of the Bridge class, with the ability to
 # account for the latency of packet serialization.
 
-class SerialLink(MemObject):
+class SerialLink(ClockedObject):
     type = 'SerialLink'
     cxx_header = "mem/serial_link.hh"
     slave = SlavePort('Slave port')
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index c9f35f3e5..976a290eb 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -44,9 +44,9 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class BaseXBar(MemObject):
+class BaseXBar(ClockedObject):
     type = 'BaseXBar'
     abstract = True
     cxx_header = "mem/xbar.hh"
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 3f2d50713..f7b02ce17 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -57,7 +57,7 @@
 using namespace std;
 
 AbstractMemory::AbstractMemory(const Params *p) :
-    MemObject(p), range(params()->range), pmemAddr(NULL),
+    ClockedObject(p), range(params()->range), pmemAddr(NULL),
     backdoor(params()->range, nullptr,
              (MemBackdoor::Flags)(MemBackdoor::Readable |
                                   MemBackdoor::Writeable)),
@@ -91,7 +91,7 @@ AbstractMemory::setBackingStore(uint8_t* pmem_addr)
 void
 AbstractMemory::regStats()
 {
-    MemObject::regStats();
+    ClockedObject::regStats();
 
     using namespace Stats;
 
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index cf9ca7439..18d8ee909 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -50,8 +50,9 @@
 #define __MEM_ABSTRACT_MEMORY_HH__
 
 #include "mem/backdoor.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/AbstractMemory.hh"
+#include "sim/clocked_object.hh"
 #include "sim/stats.hh"
 
 
@@ -98,10 +99,10 @@ class LockedAddr {
  * An abstract memory represents a contiguous block of physical
  * memory, with an associated address range, and also provides basic
  * functionality for reading and writing this memory without any
- * timing information. It is a MemObject since any subclass must have
- * at least one slave port.
+ * timing information. It is a ClockedObject since subclasses may need timing
+ * information.
  */
-class AbstractMemory : public MemObject
+class AbstractMemory : public ClockedObject
 {
   protected:
 
diff --git a/src/mem/addr_mapper.cc b/src/mem/addr_mapper.cc
index 958a8ad4c..246c039ee 100644
--- a/src/mem/addr_mapper.cc
+++ b/src/mem/addr_mapper.cc
@@ -40,7 +40,7 @@
 #include "mem/addr_mapper.hh"
 
 AddrMapper::AddrMapper(const AddrMapperParams* p)
-    : MemObject(p),
+    : SimObject(p),
       masterPort(name() + "-master", *this),
       slavePort(name() + "-slave", *this)
 {
@@ -61,7 +61,7 @@ AddrMapper::getPort(const std::string &if_name, PortID idx)
     } else if (if_name == "slave") {
         return slavePort;
     } else {
-        return MemObject::getPort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }
 
diff --git a/src/mem/addr_mapper.hh b/src/mem/addr_mapper.hh
index aaefdedc3..e6229d67a 100644
--- a/src/mem/addr_mapper.hh
+++ b/src/mem/addr_mapper.hh
@@ -40,9 +40,10 @@
 #ifndef __MEM_ADDR_MAPPER_HH__
 #define __MEM_ADDR_MAPPER_HH__
 
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/AddrMapper.hh"
 #include "params/RangeAddrMapper.hh"
+#include "sim/sim_object.hh"
 
 /**
  * An address mapper changes the packet addresses in going from the
@@ -53,7 +54,7 @@
  * currently not modified.
  */
 
-class AddrMapper : public MemObject
+class AddrMapper : public SimObject
 {
 
   public:
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 7428e7f77..9c4241097 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -77,7 +77,7 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
 }
 
 Bridge::Bridge(Params *p)
-    : MemObject(p),
+    : ClockedObject(p),
       slavePort(p->name + ".slave", *this, masterPort,
                 ticksToCycles(p->delay), p->resp_size, p->ranges),
       masterPort(p->name + ".master", *this, slavePort,
@@ -94,7 +94,7 @@ Bridge::getPort(const std::string &if_name, PortID idx)
         return slavePort;
     else
         // pass it along to our super class
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
 }
 
 void
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index b3fb90d93..16b21addf 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -54,8 +54,9 @@
 #include <deque>
 
 #include "base/types.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/Bridge.hh"
+#include "sim/clocked_object.hh"
 
 /**
  * A bridge is used to interface two different crossbars (or in general a
@@ -70,7 +71,7 @@
  * the bridge will delay accepting the packet until space becomes
  * available.
  */
-class Bridge : public MemObject
+class Bridge : public ClockedObject
 {
   protected:
 
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 0a590c2ca..b2f478472 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -43,7 +43,7 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 from m5.objects.Prefetcher import BasePrefetcher
 from m5.objects.ReplacementPolicies import *
 from m5.objects.Tags import *
@@ -72,7 +72,7 @@ class WriteAllocator(SimObject):
     block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
 
 
-class BaseCache(MemObject):
+class BaseCache(ClockedObject):
     type = 'BaseCache'
     abstract = True
     cxx_header = "mem/cache/base.hh"
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 554a61eb0..f087618c7 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -77,7 +77,7 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
 }
 
 BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
-    : MemObject(p),
+    : ClockedObject(p),
       cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
       memSidePort(p->name + ".mem_side", this, "MemSidePort"),
       mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
@@ -193,7 +193,7 @@ BaseCache::getPort(const std::string &if_name, PortID idx)
     } else if (if_name == "cpu_side") {
         return cpuSidePort;
     }  else {
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
     }
 }
 
@@ -1696,7 +1696,7 @@ BaseCache::unserialize(CheckpointIn &cp)
 void
 BaseCache::regStats()
 {
-    MemObject::regStats();
+    ClockedObject::regStats();
 
     using namespace Stats;
 
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 8d5ed11d0..b995a6e47 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -68,12 +68,12 @@
 #include "mem/cache/tags/base.hh"
 #include "mem/cache/write_queue.hh"
 #include "mem/cache/write_queue_entry.hh"
-#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/packet_queue.hh"
 #include "mem/qport.hh"
 #include "mem/request.hh"
 #include "params/WriteAllocator.hh"
+#include "sim/clocked_object.hh"
 #include "sim/eventq.hh"
 #include "sim/probe/probe.hh"
 #include "sim/serialize.hh"
@@ -91,7 +91,7 @@ struct BaseCacheParams;
 /**
  * A basic cache interface. Implements some common functions for speed.
  */
-class BaseCache : public MemObject
+class BaseCache : public ClockedObject
 {
   protected:
     /**
diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc
index f27027dfd..90268bf3f 100644
--- a/src/mem/comm_monitor.cc
+++ b/src/mem/comm_monitor.cc
@@ -49,7 +49,7 @@
 #include "sim/stats.hh"
 
 CommMonitor::CommMonitor(Params* params)
-    : MemObject(params),
+    : SimObject(params),
       masterPort(name() + "-master", *this),
       slavePort(name() + "-slave", *this),
       samplePeriodicEvent([this]{ samplePeriodic(); }, name()),
@@ -91,7 +91,7 @@ CommMonitor::getPort(const std::string &if_name, PortID idx)
     } else if (if_name == "slave") {
         return slavePort;
     } else {
-        return MemObject::getPort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }
 
@@ -381,7 +381,7 @@ CommMonitor::recvRangeChange()
 void
 CommMonitor::regStats()
 {
-    MemObject::regStats();
+    SimObject::regStats();
 
     // Initialise all the monitor stats
     using namespace Stats;
diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh
index 1eea6a535..350155924 100644
--- a/src/mem/comm_monitor.hh
+++ b/src/mem/comm_monitor.hh
@@ -46,12 +46,13 @@
 #define __MEM_COMM_MONITOR_HH__
 
 #include "base/statistics.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/CommMonitor.hh"
 #include "sim/probe/mem.hh"
+#include "sim/sim_object.hh"
 
 /**
- * The communication monitor is a MemObject which can monitor statistics of
+ * The communication monitor is a SimObject which can monitor statistics of
  * the communication happening between two ports in the memory system.
  *
  * Currently the following stats are implemented: Histograms of read/write
@@ -61,7 +62,7 @@
  * to capture the number of accesses to an address over time ("heat map").
  * All stats can be disabled from Python.
  */
-class CommMonitor : public MemObject
+class CommMonitor : public SimObject
 {
 
   public: // Construction & SimObject interfaces
@@ -83,7 +84,7 @@ class CommMonitor : public MemObject
     void startup() override;
     void regProbePoints() override;
 
-  public: // MemObject interfaces
+  public: // SimObject interfaces
     Port &getPort(const std::string &if_name,
                   PortID idx=InvalidPortID) override;
 
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 429e9ef5e..08465aa70 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -2849,7 +2849,7 @@ Port &
 DRAMCtrl::getPort(const string &if_name, PortID idx)
 {
     if (if_name != "port") {
-        return MemObject::getPort(if_name, idx);
+        return QoS::MemCtrl::getPort(if_name, idx);
     } else {
         return port;
     }
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index f0c612120..3f20bb3ec 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -340,7 +340,7 @@ Port &
 DRAMSim2::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name != "port") {
-        return MemObject::getPort(if_name, idx);
+        return AbstractMemory::getPort(if_name, idx);
     } else {
         return port;
     }
diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc
index 799f85036..d530d9ad0 100644
--- a/src/mem/external_master.cc
+++ b/src/mem/external_master.cc
@@ -52,7 +52,7 @@ std::map<std::string, ExternalMaster::Handler *>
     ExternalMaster::portHandlers;
 
 ExternalMaster::ExternalMaster(ExternalMasterParams *params) :
-    MemObject(params),
+    SimObject(params),
     externalPort(NULL),
     portName(params->name + ".port"),
     portType(params->port_type),
@@ -83,7 +83,7 @@ ExternalMaster::getPort(const std::string &if_name, PortID idx)
         }
         return *externalPort;
     } else {
-        return MemObject::getPort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }
 
diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh
index f105054b4..debc86269 100644
--- a/src/mem/external_master.hh
+++ b/src/mem/external_master.hh
@@ -60,10 +60,11 @@
 #ifndef __MEM_EXTERNAL_MASTER_HH__
 #define __MEM_EXTERNAL_MASTER_HH__
 
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/ExternalMaster.hh"
+#include "sim/sim_object.hh"
 
-class ExternalMaster : public MemObject
+class ExternalMaster : public SimObject
 {
   public:
     /** Derive from this class to create an external port interface */
diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc
index 6266f6649..ae81e1b15 100644
--- a/src/mem/external_slave.cc
+++ b/src/mem/external_slave.cc
@@ -181,7 +181,7 @@ ExternalSlave::ExternalPort::getAddrRanges() const
 }
 
 ExternalSlave::ExternalSlave(ExternalSlaveParams *params) :
-    MemObject(params),
+    SimObject(params),
     externalPort(NULL),
     portName(params->name + ".port"),
     portType(params->port_type),
@@ -216,7 +216,7 @@ ExternalSlave::getPort(const std::string &if_name, PortID idx)
         }
         return *externalPort;
     } else {
-        return MemObject::getPort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }
 
diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh
index cfe89b98a..ab33fc53b 100644
--- a/src/mem/external_slave.hh
+++ b/src/mem/external_slave.hh
@@ -60,10 +60,11 @@
 #ifndef __MEM_EXTERNAL_SLAVE_HH__
 #define __MEM_EXTERNAL_SLAVE_HH__
 
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/ExternalSlave.hh"
+#include "sim/sim_object.hh"
 
-class ExternalSlave : public MemObject
+class ExternalSlave : public SimObject
 {
   public:
     /** Derive from this class to create an external port interface */
diff --git a/src/mem/mem_checker_monitor.cc b/src/mem/mem_checker_monitor.cc
index 8364b9198..6879f951b 100644
--- a/src/mem/mem_checker_monitor.cc
+++ b/src/mem/mem_checker_monitor.cc
@@ -49,7 +49,7 @@
 #include "debug/MemCheckerMonitor.hh"
 
 MemCheckerMonitor::MemCheckerMonitor(Params* params)
-    : MemObject(params),
+    : SimObject(params),
       masterPort(name() + "-master", *this),
       slavePort(name() + "-slave", *this),
       warnOnly(params->warn_only),
@@ -81,7 +81,7 @@ MemCheckerMonitor::getPort(const std::string &if_name, PortID idx)
     } else if (if_name == "slave" || if_name == "cpu_side") {
         return slavePort;
     } else {
-        return MemObject::getPort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }
 
diff --git a/src/mem/mem_checker_monitor.hh b/src/mem/mem_checker_monitor.hh
index ba150493f..09465a236 100644
--- a/src/mem/mem_checker_monitor.hh
+++ b/src/mem/mem_checker_monitor.hh
@@ -44,14 +44,14 @@
 
 #include "base/statistics.hh"
 #include "mem/mem_checker.hh"
-#include "mem/mem_object.hh"
 #include "params/MemCheckerMonitor.hh"
+#include "sim/sim_object.hh"
 #include "sim/system.hh"
 
 /**
  * Implements a MemChecker monitor, to be inserted between two ports.
  */
-class MemCheckerMonitor : public MemObject
+class MemCheckerMonitor : public SimObject
 {
   public:
 
diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index 67a9664f8..f1a0f2151 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -43,7 +43,7 @@
 #include "params/SimpleMemDelay.hh"
 
 MemDelay::MemDelay(const MemDelayParams *p)
-    : MemObject(p),
+    : ClockedObject(p),
       masterPort(name() + "-master", *this),
       slavePort(name() + "-slave", *this),
       reqQueue(*this, masterPort),
@@ -68,7 +68,7 @@ MemDelay::getPort(const std::string &if_name, PortID idx)
     } else if (if_name == "slave") {
         return slavePort;
     } else {
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
     }
 }
 
diff --git a/src/mem/mem_delay.hh b/src/mem/mem_delay.hh
index 789d965c8..894ddc02d 100644
--- a/src/mem/mem_delay.hh
+++ b/src/mem/mem_delay.hh
@@ -40,8 +40,8 @@
 #ifndef __MEM_MEM_DELAY_HH__
 #define __MEM_MEM_DELAY_HH__
 
-#include "mem/mem_object.hh"
 #include "mem/qport.hh"
+#include "sim/clocked_object.hh"
 
 struct MemDelayParams;
 struct SimpleMemDelayParams;
@@ -61,7 +61,7 @@ struct SimpleMemDelayParams;
  *
  * NOTE: Packets may be reordered if the delays aren't constant.
  */
-class MemDelay : public MemObject
+class MemDelay : public ClockedObject
 {
 
   public:
diff --git a/src/mem/mport.hh b/src/mem/mport.hh
index 72d0b0962..6655b1143 100644
--- a/src/mem/mport.hh
+++ b/src/mem/mport.hh
@@ -43,8 +43,8 @@
 #ifndef __MEM_MPORT_HH__
 #define __MEM_MPORT_HH__
 
-#include "mem/mem_object.hh"
 #include "mem/tport.hh"
+#include "sim/sim_object.hh"
 
 /*
  * This file defines a port class which is used for sending and receiving
@@ -57,7 +57,7 @@ class MessageSlavePort : public SimpleTimingPort
 {
 
   public:
-    MessageSlavePort(const std::string &name, MemObject *owner) :
+    MessageSlavePort(const std::string &name, SimObject *owner) :
         SimpleTimingPort(name, owner)
     {}
 
@@ -75,7 +75,7 @@ class MessageMasterPort : public QueuedMasterPort
 {
   public:
 
-    MessageMasterPort(const std::string &name, MemObject *owner) :
+    MessageMasterPort(const std::string &name, SimObject *owner) :
         QueuedMasterPort(name, owner, reqQueue, snoopRespQueue),
         reqQueue(*owner, *this), snoopRespQueue(*owner, *this)
     {}
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index f942e8ddd..93b3ad5de 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -387,16 +387,16 @@ class Packet : public Printable
 
     /**
      * A virtual base opaque structure used to hold state associated
-     * with the packet (e.g., an MSHR), specific to a MemObject that
+     * with the packet (e.g., an MSHR), specific to a SimObject that
      * sees the packet. A pointer to this state is returned in the
-     * packet's response so that the MemObject in question can quickly
+     * packet's response so that the SimObject in question can quickly
      * look up the state needed to process it. A specific subclass
      * would be derived from this to carry state specific to a
      * particular sending device.
      *
-     * As multiple MemObjects may add their SenderState throughout the
+     * As multiple SimObjects may add their SenderState throughout the
      * memory system, the SenderStates create a stack, where a
-     * MemObject can add a new Senderstate, as long as the
+     * SimObject can add a new Senderstate, as long as the
      * predecessing SenderState is restored when the response comes
      * back. For this reason, the predecessor should always be
      * populated with the current SenderState of a packet before
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 933e98243..ee312eac7 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -49,7 +49,7 @@
 #include "mem/port.hh"
 
 #include "base/trace.hh"
-#include "mem/mem_object.hh"
+#include "sim/sim_object.hh"
 
 BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
     : Port(name, _id), _baseSlavePort(NULL)
@@ -92,7 +92,7 @@ BaseSlavePort::getMasterPort() const
 /**
  * Master port
  */
-MasterPort::MasterPort(const std::string& name, MemObject* _owner, PortID _id)
+MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
     : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
 {
 }
@@ -201,7 +201,7 @@ MasterPort::printAddr(Addr a)
 /**
  * Slave port
  */
-SlavePort::SlavePort(const std::string& name, MemObject* _owner, PortID id)
+SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
     : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
     owner(*_owner)
 {
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 72a02711c..76ad3bd63 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -55,7 +55,7 @@
 #include "mem/packet.hh"
 #include "sim/port.hh"
 
-class MemObject;
+class SimObject;
 
 /** Forward declaration */
 class BaseSlavePort;
@@ -123,11 +123,11 @@ class MasterPort : public BaseMasterPort
 
   protected:
 
-    MemObject& owner;
+    SimObject& owner;
 
   public:
 
-    MasterPort(const std::string& name, MemObject* _owner,
+    MasterPort(const std::string& name, SimObject* _owner,
                PortID id=InvalidPortID);
     virtual ~MasterPort();
 
@@ -317,11 +317,11 @@ class SlavePort : public BaseSlavePort
 
   protected:
 
-    MemObject& owner;
+    SimObject& owner;
 
   public:
 
-    SlavePort(const std::string& name, MemObject* _owner,
+    SlavePort(const std::string& name, SimObject* _owner,
               PortID id=InvalidPortID);
     virtual ~SlavePort();
 
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc
index 3ff2339d5..1f104e432 100644
--- a/src/mem/qos/mem_sink.cc
+++ b/src/mem/qos/mem_sink.cc
@@ -110,7 +110,7 @@ Port &
 MemSinkCtrl::getPort(const std::string &interface, PortID idx)
 {
     if (interface != "port") {
-        return MemObject::getPort(interface, idx);
+        return MemCtrl::getPort(interface, idx);
     } else {
         return port;
     }
diff --git a/src/mem/qport.hh b/src/mem/qport.hh
index 77d8dfafa..6d9655f41 100644
--- a/src/mem/qport.hh
+++ b/src/mem/qport.hh
@@ -47,6 +47,7 @@
 
 #include "mem/packet_queue.hh"
 #include "mem/port.hh"
+#include "sim/sim_object.hh"
 
 /**
  * A queued port is a port that has an infinite queue for outgoing
@@ -75,7 +76,7 @@ class QueuedSlavePort : public SlavePort
      * behaviuor in a subclass, and provide the latter to the
      * QueuePort constructor.
      */
-    QueuedSlavePort(const std::string& name, MemObject* owner,
+    QueuedSlavePort(const std::string& name, SimObject* owner,
                     RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
         SlavePort(name, owner, id), respQueue(resp_queue)
     { }
@@ -128,7 +129,7 @@ class QueuedMasterPort : public MasterPort
      * behaviuor in a subclass, and provide the latter to the
      * QueuePort constructor.
      */
-    QueuedMasterPort(const std::string& name, MemObject* owner,
+    QueuedMasterPort(const std::string& name, SimObject* owner,
                      ReqPacketQueue &req_queue,
                      SnoopRespPacketQueue &snoop_resp_queue,
                      PortID id = InvalidPortID) :
diff --git a/src/mem/ruby/network/dummy_port.hh b/src/mem/ruby/network/dummy_port.hh
index ca1ef4155..2d675aa60 100644
--- a/src/mem/ruby/network/dummy_port.hh
+++ b/src/mem/ruby/network/dummy_port.hh
@@ -43,7 +43,7 @@ class RubyDummyPort : public Port
         // No need to connect anything here currently. MessageBuffer
         // port connections only serve to print the connections in
         // the config output.
-        // TODO: Add real ports to MessageBuffers and use MemObject connect
+        // TODO: Add real ports to MessageBuffers and use SimObject connect
         // code below to bind MessageBuffer senders and receivers
     }
     void unbind() override {}
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index fa1c936b7..68edcba59 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -49,7 +49,7 @@
 #include "sim/system.hh"
 
 AbstractController::AbstractController(const Params *p)
-    : MemObject(p), Consumer(this), m_version(p->version),
+    : ClockedObject(p), Consumer(this), m_version(p->version),
       m_clusterID(p->cluster_id),
       m_masterId(p->system->getMasterId(this)), m_is_blocking(false),
       m_number_of_TBEs(p->number_of_TBEs),
@@ -90,7 +90,7 @@ AbstractController::resetStats()
 void
 AbstractController::regStats()
 {
-    MemObject::regStats();
+    ClockedObject::regStats();
 
     m_fully_busy_cycles
         .name(name() + ".fully_busy_cycles")
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 5e39a28d2..4d0654698 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -47,7 +47,6 @@
 
 #include "base/addr_range.hh"
 #include "base/callback.hh"
-#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/qport.hh"
@@ -59,6 +58,7 @@
 #include "mem/ruby/network/MessageBuffer.hh"
 #include "mem/ruby/system/CacheRecorder.hh"
 #include "params/RubyController.hh"
+#include "sim/clocked_object.hh"
 
 class Network;
 class GPUCoalescer;
@@ -70,7 +70,7 @@ class RejectException: public std::exception
     { return "Port rejected message based on type"; }
 };
 
-class AbstractController : public MemObject, public Consumer
+class AbstractController : public ClockedObject, public Consumer
 {
   public:
     typedef RubyControllerParams Params;
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index 0eb704916..4d3c1900e 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -41,9 +41,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class RubyController(MemObject):
+class RubyController(ClockedObject):
     type = 'RubyController'
     cxx_class = 'AbstractController'
     cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 795b473c7..ff3bbe8f0 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -52,7 +52,7 @@
 #include "sim/system.hh"
 
 RubyPort::RubyPort(const Params *p)
-    : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
+    : ClockedObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
       m_controller(NULL), m_mandatory_q_ptr(NULL),
       m_usingRubyTester(p->using_ruby_tester), system(p->system),
       pioMasterPort(csprintf("%s.pio-master-port", name()), this),
@@ -117,7 +117,7 @@ RubyPort::getPort(const std::string &if_name, PortID idx)
     }
 
     // pass it along to our super class
-    return MemObject::getPort(if_name, idx);
+    return ClockedObject::getPort(if_name, idx);
 }
 
 RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 922b3a973..20bc03a07 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -49,13 +49,13 @@
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
 #include "mem/ruby/system/RubySystem.hh"
-#include "mem/mem_object.hh"
 #include "mem/tport.hh"
 #include "params/RubyPort.hh"
+#include "sim/clocked_object.hh"
 
 class AbstractController;
 
-class RubyPort : public MemObject
+class RubyPort : public ClockedObject
 {
   public:
     class MemMasterPort : public QueuedMasterPort
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 35460438c..2aede349d 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -29,9 +29,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class RubyPort(MemObject):
+class RubyPort(ClockedObject):
    type = 'RubyPort'
    abstract = True
    cxx_header = "mem/ruby/system/RubyPort.hh"
diff --git a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
index 77ee60554..fa50c95dc 100644
--- a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
+++ b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
@@ -33,7 +33,6 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5.objects.MemObject import MemObject
 from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class WeightedLRUReplacementPolicy(ReplacementPolicy):
diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc
index 438fb0e68..b39ac5946 100644
--- a/src/mem/serial_link.cc
+++ b/src/mem/serial_link.cc
@@ -82,7 +82,7 @@ SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string&
 }
 
 SerialLink::SerialLink(SerialLinkParams *p)
-    : MemObject(p),
+    : ClockedObject(p),
       slavePort(p->name + ".slave", *this, masterPort,
                 ticksToCycles(p->delay), p->resp_size, p->ranges),
       masterPort(p->name + ".master", *this, slavePort,
@@ -102,7 +102,7 @@ SerialLink::getPort(const std::string &if_name, PortID idx)
         return slavePort;
     else
         // pass it along to our super class
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
 }
 
 void
diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh
index 0bb1692ed..3dac18045 100644
--- a/src/mem/serial_link.hh
+++ b/src/mem/serial_link.hh
@@ -56,8 +56,9 @@
 #include <deque>
 
 #include "base/types.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/SerialLink.hh"
+#include "sim/clocked_object.hh"
 
 /**
  * SerialLink is a simple variation of the Bridge class, with the ability to
@@ -66,7 +67,7 @@
  * whole packet to start the serialization. But the deserializer waits for the
  * complete packet to check its integrity first.
   */
-class SerialLink : public MemObject
+class SerialLink : public ClockedObject
 {
   protected:
 
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index fcc1cff23..9e7dfc815 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -245,7 +245,7 @@ Port &
 SimpleMemory::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name != "port") {
-        return MemObject::getPort(if_name, idx);
+        return AbstractMemory::getPort(if_name, idx);
     } else {
         return port;
     }
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 9f0f08814..4de495e22 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -42,11 +42,10 @@
  */
 
 #include "mem/tport.hh"
-
-#include "mem/mem_object.hh"
+#include "sim/sim_object.hh"
 
 SimpleTimingPort::SimpleTimingPort(const std::string& _name,
-                                   MemObject* _owner) :
+                                   SimObject* _owner) :
     QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
 {
 }
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index d7e4bbc74..d62b1405d 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -52,6 +52,8 @@
 
 #include "mem/qport.hh"
 
+class SimObject;
+
 /**
  * The simple timing port uses a queued port to implement
  * recvFunctional and recvTimingReq through recvAtomic. It is always a
@@ -99,7 +101,7 @@ class SimpleTimingPort : public QueuedSlavePort
      * @param name port name
      * @param owner structural owner
      */
-    SimpleTimingPort(const std::string& name, MemObject* owner);
+    SimpleTimingPort(const std::string& name, SimObject* owner);
 
     virtual ~SimpleTimingPort() { }
 
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 9328c2990..de32c0b32 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -56,7 +56,7 @@
 #include "debug/XBar.hh"
 
 BaseXBar::BaseXBar(const BaseXBarParams *p)
-    : MemObject(p),
+    : ClockedObject(p),
       frontendLatency(p->frontend_latency),
       forwardLatency(p->forward_latency),
       responseLatency(p->response_latency),
@@ -88,7 +88,7 @@ BaseXBar::getPort(const std::string &if_name, PortID idx)
         // the slave port index translates directly to the vector position
         return *slavePorts[idx];
     } else {
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
     }
 }
 
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index b688f309a..8de7af46f 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -56,9 +56,9 @@
 
 #include "base/addr_range_map.hh"
 #include "base/types.hh"
-#include "mem/mem_object.hh"
 #include "mem/qport.hh"
 #include "params/BaseXBar.hh"
+#include "sim/clocked_object.hh"
 #include "sim/stats.hh"
 
 /**
@@ -70,7 +70,7 @@
  * The BaseXBar is responsible for the basic flow control (busy or
  * not), the administration of retries, and the address decoding.
  */
-class BaseXBar : public MemObject
+class BaseXBar : public ClockedObject
 {
 
   protected: