python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

39 files changed, 65 insertions, 57 deletions

diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index d5b34bbd0..5bffc30af 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class AbstractMemory(MemObject):
     type = 'AbstractMemory'
diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index f6e943ed1..a1ddaeb7a 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # An address mapper changes the packet addresses in going from the
 # slave port side of the mapper to the master port side. When the
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index e488871a4..34af552e3 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index aa8da62ed..fc53ef1f0 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -38,8 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from System import System
+from m5.objects.MemObject import MemObject
+from m5.objects.System import System
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index fa04c9f39..93ea7d56f 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -46,8 +46,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from AbstractMemory import *
-from QoSMemCtrl import *
+from m5.objects.AbstractMemory import *
+from m5.objects.QoSMemCtrl import *
 
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index 44b49971a..883e27727 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalMaster(MemObject):
     type = 'ExternalMaster'
diff --git a/src/mem/ExternalSlave.py b/src/mem/ExternalSlave.py
index 15f529de6..7be5fd8a9 100644
--- a/src/mem/ExternalSlave.py
+++ b/src/mem/ExternalSlave.py
@@ -36,7 +36,7 @@
 # Authors: Andrew Bardsley
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalSlave(MemObject):
     type = 'ExternalSlave'
diff --git a/src/mem/HMCController.py b/src/mem/HMCController.py
index e52438e98..bb6171f17 100644
--- a/src/mem/HMCController.py
+++ b/src/mem/HMCController.py
@@ -39,7 +39,7 @@
 # Authors: Erfan Azarkhish
 
 from m5.params import *
-from XBar import *
+from m5.objects.XBar import *
 
 # References:
 # [1] http://www.open-silicon.com/open-silicon-ips/hmc/
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 5126f4364..7460cd13b 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -35,7 +35,7 @@
 #
 # Authors: Marco Elver
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index b48866815..415cef4ce 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class MemDelay(MemObject):
     type = 'MemDelay'
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
index 0827218aa..42d561d73 100644
--- a/src/mem/MemObject.py
+++ b/src/mem/MemObject.py
@@ -26,7 +26,7 @@
 #
 # Authors: Ron Dreslinski
 
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
 
 class MemObject(ClockedObject):
     type = 'MemObject'
diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index fd9b0ff6b..02dcd4c7e 100644
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -42,7 +42,7 @@
 #          Erfan Azarkhish
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # SerialLink is a simple variation of the Bridge class, with the ability to
 # account for the latency of packet serialization.
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 0a90eaa7c..34cc186f4 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from AbstractMemory import *
+from m5.objects.AbstractMemory import *
 
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index 655d9808a..c9f35f3e5 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -39,12 +39,13 @@
 # Authors: Nathan Binkert
 #          Andreas Hansson
 
-from MemObject import MemObject
-from System import System
+from m5.objects.System import System
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
+from m5.objects.MemObject import MemObject
+
 class BaseXBar(MemObject):
     type = 'BaseXBar'
     abstract = True
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 8ffab911b..0a590c2ca 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -42,10 +42,11 @@
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from MemObject import MemObject
-from Prefetcher import BasePrefetcher
-from ReplacementPolicies import *
-from Tags import *
+
+from m5.objects.MemObject import MemObject
+from m5.objects.Prefetcher import BasePrefetcher
+from m5.objects.ReplacementPolicies import *
+from m5.objects.Tags import *
 
 
 # Enum for cache clusivity, currently mostly inclusive or mostly
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 082590853..827a66b0f 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -39,12 +39,13 @@
 # Authors: Ron Dreslinski
 #          Mitch Hayenga
 
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
 from m5.SimObject import *
 from m5.params import *
 from m5.proxy import *
-from ReplacementPolicies import *
+
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
+from m5.objects.ReplacementPolicies import *
 
 class HWPProbeEvent(object):
     def __init__(self, prefetcher, obj, *listOfNames):
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index f2658f4f8..9ac240d13 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -37,8 +37,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
 
 class BaseTags(ClockedObject):
     type = 'BaseTags'
diff --git a/src/mem/probes/MemFootprintProbe.py b/src/mem/probes/MemFootprintProbe.py
index 7a6551207..64b79fe16 100644
--- a/src/mem/probes/MemFootprintProbe.py
+++ b/src/mem/probes/MemFootprintProbe.py
@@ -38,7 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class MemFootprintProbe(BaseMemProbe):
     type = "MemFootprintProbe"
diff --git a/src/mem/probes/MemTraceProbe.py b/src/mem/probes/MemTraceProbe.py
index 8daf94dbd..9dfd0eb51 100644
--- a/src/mem/probes/MemTraceProbe.py
+++ b/src/mem/probes/MemTraceProbe.py
@@ -37,7 +37,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class MemTraceProbe(BaseMemProbe):
     type = 'MemTraceProbe'
diff --git a/src/mem/probes/StackDistProbe.py b/src/mem/probes/StackDistProbe.py
index 431e86463..89a752d74 100644
--- a/src/mem/probes/StackDistProbe.py
+++ b/src/mem/probes/StackDistProbe.py
@@ -38,7 +38,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class StackDistProbe(BaseMemProbe):
     type = 'StackDistProbe'
diff --git a/src/mem/qos/QoSMemCtrl.py b/src/mem/qos/QoSMemCtrl.py
index 185856553..dbf881ca0 100644
--- a/src/mem/qos/QoSMemCtrl.py
+++ b/src/mem/qos/QoSMemCtrl.py
@@ -36,8 +36,8 @@
 # Authors: Matteo Andreozzi
 
 from m5.params import *
-from AbstractMemory import AbstractMemory
-from QoSTurnaround import *
+from m5.objects.AbstractMemory import AbstractMemory
+from m5.objects.QoSTurnaround import *
 
 # QoS Queue Selection policy used to select packets among same-QoS queues
 class QoSQPolicy(Enum): vals = ["fifo", "lifo", "lrg"]
diff --git a/src/mem/qos/QoSMemSinkCtrl.py b/src/mem/qos/QoSMemSinkCtrl.py
index 00f19ef7d..572cad5c4 100644
--- a/src/mem/qos/QoSMemSinkCtrl.py
+++ b/src/mem/qos/QoSMemSinkCtrl.py
@@ -36,7 +36,7 @@
 # Author: Matteo Andreozzi
 
 from m5.params import *
-from QoSMemCtrl import *
+from m5.objects.QoSMemCtrl import *
 
 class QoSMemSinkCtrl(QoSMemCtrl):
     type = 'QoSMemSinkCtrl'
diff --git a/src/mem/ruby/network/BasicRouter.py b/src/mem/ruby/network/BasicRouter.py
index 68a7b1d8b..e121048d4 100644
--- a/src/mem/ruby/network/BasicRouter.py
+++ b/src/mem/ruby/network/BasicRouter.py
@@ -28,7 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
+
+from m5.objects.ClockedObject import ClockedObject
 
 class BasicRouter(ClockedObject):
     type = 'BasicRouter'
diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py
index da0a788b5..861fd791d 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -28,8 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicLink
 
 class RubyNetwork(ClockedObject):
     type = 'RubyNetwork'
diff --git a/src/mem/ruby/network/garnet2.0/GarnetLink.py b/src/mem/ruby/network/garnet2.0/GarnetLink.py
index fc5632d49..0e7c4d1c6 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetLink.py
+++ b/src/mem/ruby/network/garnet2.0/GarnetLink.py
@@ -30,8 +30,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
 
 class NetworkLink(ClockedObject):
     type = 'NetworkLink'
diff --git a/src/mem/ruby/network/garnet2.0/GarnetNetwork.py b/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
index 00213d60f..04c0ef46b 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
+++ b/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
@@ -30,9 +30,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from ClockedObject import ClockedObject
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.ClockedObject import ClockedObject
 
 class GarnetNetwork(RubyNetwork):
     type = 'GarnetNetwork'
diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py
index 716a21eec..2832b1c5c 100644
--- a/src/mem/ruby/network/simple/SimpleLink.py
+++ b/src/mem/ruby/network/simple/SimpleLink.py
@@ -30,7 +30,7 @@
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
 
 class SimpleExtLink(BasicExtLink):
     type = 'SimpleExtLink'
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py
index 3d6f7e854..e7a79492b 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.py
+++ b/src/mem/ruby/network/simple/SimpleNetwork.py
@@ -29,9 +29,10 @@
 
 from m5.params import *
 from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from MessageBuffer import MessageBuffer
+
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.MessageBuffer import MessageBuffer
 
 class SimpleNetwork(RubyNetwork):
     type = 'SimpleNetwork'
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index 39a0ea912..0eb704916 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -41,7 +41,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class RubyController(MemObject):
     type = 'RubyController'
diff --git a/src/mem/ruby/structures/LRUReplacementPolicy.py b/src/mem/ruby/structures/LRUReplacementPolicy.py
index 2b4a263b7..9c36b5f51 100644
--- a/src/mem/ruby/structures/LRUReplacementPolicy.py
+++ b/src/mem/ruby/structures/LRUReplacementPolicy.py
@@ -31,7 +31,7 @@
 
 from m5.params import *
 from m5.SimObject import SimObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class LRUReplacementPolicy(ReplacementPolicy):
     type = 'LRUReplacementPolicy'
diff --git a/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py b/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
index d922007f5..2b892d47a 100644
--- a/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
+++ b/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
@@ -27,7 +27,7 @@
 #
 # Author: Derek Hower
 
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class PseudoLRUReplacementPolicy(ReplacementPolicy):
     type = 'PseudoLRUReplacementPolicy'
diff --git a/src/mem/ruby/structures/RubyCache.py b/src/mem/ruby/structures/RubyCache.py
index 9fc4726b0..cf8410c6d 100644
--- a/src/mem/ruby/structures/RubyCache.py
+++ b/src/mem/ruby/structures/RubyCache.py
@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
+from m5.objects.PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
 from m5.SimObject import SimObject
 
 class RubyCache(SimObject):
diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py
index 18bb3dc69..00a933d8c 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.py
+++ b/src/mem/ruby/structures/RubyPrefetcher.py
@@ -27,10 +27,11 @@
 # Authors: Nilay Vaish
 
 from m5.SimObject import SimObject
-from System import System
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.System import System
+
 class Prefetcher(SimObject):
     type = 'Prefetcher'
     cxx_class = 'Prefetcher'
diff --git a/src/mem/ruby/system/GPUCoalescer.py b/src/mem/ruby/system/GPUCoalescer.py
index 87ee3b221..ec6429342 100644
--- a/src/mem/ruby/system/GPUCoalescer.py
+++ b/src/mem/ruby/system/GPUCoalescer.py
@@ -34,7 +34,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Sequencer import *
+
+from m5.objects.Sequencer import *
 
 class RubyGPUCoalescer(RubyPort):
    type = 'RubyGPUCoalescer'
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index 5dcfe2f81..02d2890e2 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -28,8 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
-from SimpleMemory import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.SimpleMemory import *
 
 class RubySystem(ClockedObject):
     type = 'RubySystem'
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 22d545d30..35460438c 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class RubyPort(MemObject):
    type = 'RubyPort'
diff --git a/src/mem/ruby/system/VIPERCoalescer.py b/src/mem/ruby/system/VIPERCoalescer.py
index 280a33382..85370f6df 100644
--- a/src/mem/ruby/system/VIPERCoalescer.py
+++ b/src/mem/ruby/system/VIPERCoalescer.py
@@ -34,7 +34,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from GPUCoalescer import *
+from m5.objects.GPUCoalescer import *
 
 class VIPERCoalescer(RubyGPUCoalescer):
     type = 'VIPERCoalescer'
diff --git a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
index 80f3d6981..77ee60554 100644
--- a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
+++ b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
@@ -33,8 +33,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.MemObject import MemObject
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class WeightedLRUReplacementPolicy(ReplacementPolicy):
     type = "WeightedLRUReplacementPolicy"
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index e63f6fc60..cbcc7924a 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -226,7 +226,7 @@ class StateMachine(Symbol):
         code('''
 from m5.params import *
 from m5.SimObject import SimObject
-from Controller import RubyController
+from m5.objects.Controller import RubyController
 
 class $py_ident(RubyController):
     type = '$py_ident'