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authorRadhika Jagtap <radhika.jagtap@ARM.com>2015-12-07 16:42:15 -0600
committerRadhika Jagtap <radhika.jagtap@ARM.com>2015-12-07 16:42:15 -0600
commitde4dc50e9561ab789db01eb4adea1522de623782 (patch)
tree2cd8c379d8621a78bc87109d107f4d1624222ebd /src/proto/packet.proto
parenteb19fc29761a99ff7d5a5e4588866b487a2082ee (diff)
downloadgem5-de4dc50e9561ab789db01eb4adea1522de623782.tar.xz
proto, probe: Add elastic trace probe to o3 cpu
The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU. The notify method is called on a probe point typically when an instruction successfully progresses through that stage. As different listener methods mapped to the different probe points execute, relevant information about the instruction, e.g. timestamps and register accesses, are captured and stored in temporary InstExecInfo class objects. When the instruction progresses through the commit stage, the timing and the dependency information about the instruction is finalised and encapsulated in a struct called TraceInfo. TraceInfo objects are collected in a list instead of writing them out to the trace file one a time. This is required as the trace is processed in chunks to evaluate order dependencies and computational delay in case an instruction does not have any register dependencies. By this we achieve a simpler algorithm during replay because every record in the trace can be hooked onto a record in its past. The instruction dependency trace is written out as a protobuf format file. A second trace containing fetch requests at absolute timestamps is written to a separate protobuf format file. If the instruction is not executed then it is not added to the trace. The code checks if the instruction had a fault, if it predicated false and thus previous register values were restored or if it was a load/store that did not have a request (e.g. when the size of the request is zero). In all these cases the instruction is set as executed by the Execute stage and is picked up by the commit probe listener. But a request is not issued and registers are not written. So practically, skipping these should not hurt the dependency modelling. If squashing results in squashing younger instructions, it may happen that the squash probe discards the inst and removes it from the temporary store but execute stage deals with the instruction in the next cycle which results in the execute probe seeing this inst as 'new' inst. A sequence number of the last processed trace record is used to trap these cases and not add to the temporary store. The elastic instruction trace and fetch request trace can be read in and played back by the TraceCPU.
Diffstat (limited to 'src/proto/packet.proto')
-rw-r--r--src/proto/packet.proto3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/proto/packet.proto b/src/proto/packet.proto
index d27599691..c07206742 100644
--- a/src/proto/packet.proto
+++ b/src/proto/packet.proto
@@ -55,6 +55,8 @@ message PacketHeader {
// not, etc. An optional id field is added for generic use to identify
// the packet or the "owner" of the packet. An example of the latter
// is the sequential id of an instruction, or the master id etc.
+// An optional field for PC of the instruction for which this request is made
+// is provided.
message Packet {
required uint64 tick = 1;
required uint32 cmd = 2;
@@ -62,4 +64,5 @@ message Packet {
required uint32 size = 4;
optional uint32 flags = 5;
optional uint64 pkt_id = 6;
+ optional uint64 pc = 7;
}