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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-19 21:49:08 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-02-07 16:14:39 +0000 |
| commit | c364f58da916a6a1cb66c3e0276e898d77e1021b (patch) | |
| tree | acb02a2876489805fa17db918f20ef5693f62b0a /src/python/SConscript | |
| parent | 4d9811cc5fd36a972e340ad82b14ab0ccaeb5cfa (diff) | |
| download | gem5-c364f58da916a6a1cb66c3e0276e898d77e1021b.tar.xz | |
arch-arm: Turn dc ivac to dc civac when some conditions are met
The Arm ARM defines that at EL1 a data cache invalidate instruction
performs a data cache clean and invalidate operation if all of the
following apply:
* EL2 is implemented,
* HCR_EL2.VM is set to 1,
* SCR_EL3.NS is set to 1 or EL3 is not implemented.
This changeset implements this behavior.
Change-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7826
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/python/SConscript')
0 files changed, 0 insertions, 0 deletions