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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-02-14 17:39:37 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-19 09:06:57 +0000 |
| commit | 150104648f713fcf45a1ea423468948d1dc509fc (patch) | |
| tree | cd7652bcd017cde85d71a2e4a84bbc5637ef266b /src/python/m5/SimObject.py | |
| parent | 1bc41027938fd8b6a0664c0b1321c90d23538584 (diff) | |
| download | gem5-150104648f713fcf45a1ea423468948d1dc509fc.tar.xz | |
cpu: Add ISA* getter in Thread interface
This patch is adding a ISA* getter to the TC interface
Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
Reviewed-on: https://gem5-review.googlesource.com/c/16462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/python/m5/SimObject.py')
0 files changed, 0 insertions, 0 deletions