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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:09 -0600 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:09 -0600 |
| commit | 55cf3f4ac11668c4da71411a4221cc8c84298b1a (patch) | |
| tree | 09bcea86e48b63ba7984decf7949835351286db8 /src/python/m5/SimObject.py | |
| parent | 2208ea049f60618e432c69c065926bcbc810581a (diff) | |
| download | gem5-55cf3f4ac11668c4da71411a4221cc8c84298b1a.tar.xz | |
MEM: Removing the default port peer from Python ports
In preparation for the introduction of Master and Slave ports, this
patch removes the default port parameter in the Python port and thus
forces the argument list of the Port to contain only the
description. The drawback at this point is that the config port and
dma port of PCI and DMA devices have to be connected explicitly. This
is key for future diversification as the pio and config port are
slaves, but the dma port is a master.
Diffstat (limited to 'src/python/m5/SimObject.py')
| -rw-r--r-- | src/python/m5/SimObject.py | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 47ca32af2..84d70d663 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -273,8 +273,6 @@ class MetaSimObject(type): assert(not hasattr(port, 'name')) port.name = name cls._ports[name] = port - if hasattr(port, 'default'): - cls._cls_get_port_ref(name).connect(port.default) # same as _get_port_ref, effectively, but for classes def _cls_get_port_ref(cls, attr): |