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author | Alec Roelke <ar4jc@virginia.edu> | 2017-04-09 15:23:23 -0400 |
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committer | Alec Roelke <ar4jc@virginia.edu> | 2017-05-15 19:30:14 +0000 |
commit | c8c406bc305a6bf52304d5f158f5d8def0dea51f (patch) | |
tree | e0a014c7898055ce4ca13f00fe685c9fff0dce85 /src/python/m5/SimObject.py | |
parent | 8ced1bd0b0f9890992bcf9f517df5e33839621c7 (diff) | |
download | gem5-c8c406bc305a6bf52304d5f158f5d8def0dea51f.tar.xz |
cpu: fix problem with forwarding and locked load
If a (regular) store is followed closely enough by a locked load that
overlaps, the LSQ will forward the store's data to the locked load and
never tell the cache about the locked load. As a result, the cache will
not lock the address and all future store-conditional requests on that
address will fail. This patch fixes that by preventing forwarding if
the memory request is a locked load and adding another case to the LSQ
forwarding logic that delays the locked load request if a store in the
LSQ contains all or part of the data that is requested.
[Merge second and last if blocks because their bodies are the same.]
Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841
Reviewed-on: https://gem5-review.googlesource.com/2400
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/python/m5/SimObject.py')
0 files changed, 0 insertions, 0 deletions