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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-12-02 06:08:19 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-12-02 06:08:19 -0500 |
| commit | 5d22250845f6160bb0529ab510918f56a5c30f94 (patch) | |
| tree | 4c060e56a983211a3490e4010d56e2d41c322fa1 /src/python/m5/SimObject.py | |
| parent | 7ca27dd3ccc2bcd3b77480179030d07f50c3d2d9 (diff) | |
| download | gem5-5d22250845f6160bb0529ab510918f56a5c30f94.tar.xz | |
mem: Support WriteInvalidate (again)
This patch takes a clean-slate approach to providing WriteInvalidate
(write streaming, full cache line writes without first reading)
support.
Unlike the prior attempt, which took an aggressive approach of directly
writing into the cache before handling the coherence actions, this
approach follows the existing cache flows as closely as possible.
Diffstat (limited to 'src/python/m5/SimObject.py')
0 files changed, 0 insertions, 0 deletions