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authorAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:02 -0500
committerAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:02 -0500
commit050f24c7964cbe65633261e431e1105d1d5e8070 (patch)
treee4d2b820be4e83087b0b21164f528f494b501ad9 /src/python/m5/SimObject.py
parentaae6134b5487e02a90445d1b2146583740658b09 (diff)
downloadgem5-050f24c7964cbe65633261e431e1105d1d5e8070.tar.xz
sim: Add drain methods to request additional cleanup operations
This patch adds the following two methods to the Drainable base class: memWriteback() - Write back all dirty cache lines to memory using functional accesses. memInvalidate() - Invalidate memory system buffers. Dirty data won't be written back. Specifying calling memWriteback() after draining will allow us to checkpoint systems with caches. memInvalidate() can be used to drop memory system buffers in preparation for switching to an accelerated CPU model that bypasses the gem5 memory system (e.g., hardware virtualized CPUs). Note: This patch only adds the methods to Drainable, the code for flushing the TLB and the cache is committed separately.
Diffstat (limited to 'src/python/m5/SimObject.py')
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