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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-08-17 05:08:50 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-08-17 05:08:50 -0700
commit5ea906ba1625266ee80968d70e0c218adedcce9f (patch)
treea28387572527f0dac40d677a8320b797dcc2a137 /src/python/m5/SimObject.py
parentc2cce96a0bb4878a9e6a4ae635096b5ce62e41c3 (diff)
downloadgem5-5ea906ba1625266ee80968d70e0c218adedcce9f.tar.xz
sim: move iterating over SimObjects into Python.
Diffstat (limited to 'src/python/m5/SimObject.py')
-rw-r--r--src/python/m5/SimObject.py46
1 files changed, 11 insertions, 35 deletions
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 69f79ed61..a3905949a 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -530,7 +530,8 @@ class SimObject(object):
# If the attribute exists on the C++ object, transparently
# forward the reference there. This is typically used for
# SWIG-wrapped methods such as init(), regStats(),
- # regFormulas(), resetStats(), and startup().
+ # regFormulas(), resetStats(), startup(), drain(), and
+ # resume().
if self._ccObject and hasattr(self._ccObject, attr):
return getattr(self._ccObject, attr)
@@ -660,7 +661,7 @@ class SimObject(object):
def unproxy(self, base):
return self
- def unproxy_all(self):
+ def unproxyParams(self):
for param in self._params.iterkeys():
value = self._values.get(param)
if value != None and isproxy(value):
@@ -681,12 +682,6 @@ class SimObject(object):
if port != None:
port.unproxy(self)
- # Unproxy children in sorted order for determinism also.
- child_names = self._children.keys()
- child_names.sort()
- for child in child_names:
- self._children[child].unproxy_all()
-
def print_ini(self, ini_file):
print >>ini_file, '[' + self.path() + ']' # .ini section header
@@ -717,9 +712,6 @@ class SimObject(object):
print >>ini_file # blank line between objects
- for child in child_names:
- self._children[child].print_ini(ini_file)
-
def getCCParams(self):
if self._ccParams:
return self._ccParams
@@ -774,39 +766,25 @@ class SimObject(object):
% self.path()
return self._ccObject
- # Call C++ to create C++ object corresponding to this object and
- # (recursively) all its children
+ def descendants(self):
+ yield self
+ for child in self._children.itervalues():
+ for obj in child.descendants():
+ yield obj
+
+ # Call C++ to create C++ object corresponding to this object
def createCCObject(self):
self.getCCParams()
self.getCCObject() # force creation
- for child in self._children.itervalues():
- child.createCCObject()
def getValue(self):
return self.getCCObject()
# Create C++ port connections corresponding to the connections in
- # _port_refs (& recursively for all children)
+ # _port_refs
def connectPorts(self):
for portRef in self._port_refs.itervalues():
portRef.ccConnect()
- for child in self._children.itervalues():
- child.connectPorts()
-
- def startDrain(self, drain_event, recursive):
- count = 0
- if isinstance(self, SimObject):
- count += self._ccObject.drain(drain_event)
- if recursive:
- for child in self._children.itervalues():
- count += child.startDrain(drain_event, True)
- return count
-
- def resume(self):
- if isinstance(self, SimObject):
- self._ccObject.resume()
- for child in self._children.itervalues():
- child.resume()
def getMemoryMode(self):
if not isinstance(self, m5.objects.System):
@@ -820,8 +798,6 @@ class SimObject(object):
# setMemoryMode directly from self._ccObject results in calling
# SimObject::setMemoryMode, not the System::setMemoryMode
self._ccObject.setMemoryMode(mode)
- for child in self._children.itervalues():
- child.changeTiming(mode)
def takeOverFrom(self, old_cpu):
self._ccObject.takeOverFrom(old_cpu._ccObject)