summaryrefslogtreecommitdiff
path: root/src/python/m5/objects/BaseCPU.py
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-10-12 10:58:45 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-12 10:58:45 -0400
commit866cfaf9dc596d8547e14bc2133fb962776572a7 (patch)
tree19b82a8021533e8bc2e35f14fb0b6a0440756814 /src/python/m5/objects/BaseCPU.py
parent6a31898a88a9ecced399ccf50636831c21d4a75e (diff)
parent78aec04b660544ea7af80d76912b4422c4426602 (diff)
downloadgem5-866cfaf9dc596d8547e14bc2133fb962776572a7.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
Diffstat (limited to 'src/python/m5/objects/BaseCPU.py')
-rw-r--r--src/python/m5/objects/BaseCPU.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 0b887cceb..b6dc08e46 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -11,10 +11,11 @@ class BaseCPU(SimObject):
mem = Param.MemObject("memory")
system = Param.System(Parent.any, "system object")
+ cpu_id = Param.Int("CPU identifier")
+
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
- cpu_id = Param.Int(-1, "CPU identifier")
else:
workload = VectorParam.Process("processes to run")