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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-08 16:18:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-08 16:18:10 -0500 |
| commit | f720029e97358b2f69ea0ecaace89d5c2ccc6bfe (patch) | |
| tree | 49f739cbc78b842fc303c1a1296d293ca03ec961 /src/python/m5/objects/BaseCPU.py | |
| parent | 5b90922ad59189f5967dc97a00bbfead062f4ba3 (diff) | |
| parent | 74745cfeac4f4de4613d8faed77aa7e3c06cbca4 (diff) | |
| download | gem5-f720029e97358b2f69ea0ecaace89d5c2ccc6bfe.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem/
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
--HG--
extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
Diffstat (limited to 'src/python/m5/objects/BaseCPU.py')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index b6dc08e46..4e34e8a4e 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -8,7 +8,6 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") cpu_id = Param.Int("CPU identifier") @@ -47,7 +46,6 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] -# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) |