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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-30 16:25:35 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-30 16:25:35 -0400 |
commit | 1bdc65b00f40b20dc5c7e97d3c8d8e4b311230a8 (patch) | |
tree | 0fe0173bf6a5d9c173d565f85698eb6a7b2e2e48 /src/python/m5/objects/BaseCPU.py | |
parent | dea1a19b2de2fe031f714904c5247cf27b363237 (diff) | |
download | gem5-1bdc65b00f40b20dc5c7e97d3c8d8e4b311230a8.tar.xz |
First pass, now compiles with current head of tree.
Compile and initialization work, still working on functionality.
src/mem/cache/base_cache.cc:
Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects.
Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
Update for newmem
--HG--
extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb
Diffstat (limited to 'src/python/m5/objects/BaseCPU.py')
0 files changed, 0 insertions, 0 deletions