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author | Nathan Binkert <binkertn@umich.edu> | 2007-05-27 19:21:17 -0700 |
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committer | Nathan Binkert <binkertn@umich.edu> | 2007-05-27 19:21:17 -0700 |
commit | 35147170f91ccbc73d3e75440a5301f758e54dfc (patch) | |
tree | 1a480271d5dd6c4a35e2bffc296c7de407e0fb2b /src/python/m5/objects/BaseCPU.py | |
parent | 4f0f217c1b6a8c888ff8a1c60d1eb36cbdf14490 (diff) | |
download | gem5-35147170f91ccbc73d3e75440a5301f758e54dfc.tar.xz |
Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
Diffstat (limited to 'src/python/m5/objects/BaseCPU.py')
-rw-r--r-- | src/python/m5/objects/BaseCPU.py | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py deleted file mode 100644 index 986220c3f..000000000 --- a/src/python/m5/objects/BaseCPU.py +++ /dev/null @@ -1,73 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env -from AlphaTLB import AlphaDTB, AlphaITB -from SparcTLB import SparcDTB, SparcITB -from Bus import Bus -import sys - -class BaseCPU(SimObject): - type = 'BaseCPU' - abstract = True - - system = Param.System(Parent.any, "system object") - cpu_id = Param.Int("CPU identifier") - - if build_env['FULL_SYSTEM']: - do_quiesce = Param.Bool(True, "enable quiesce instructions") - do_checkpoint_insts = Param.Bool(True, - "enable checkpoint pseudo instructions") - do_statistics_insts = Param.Bool(True, - "enable statistics pseudo instructions") - - if build_env['TARGET_ISA'] == 'sparc': - dtb = Param.SparcDTB(SparcDTB(), "Data TLB") - itb = Param.SparcITB(SparcITB(), "Instruction TLB") - elif build_env['TARGET_ISA'] == 'alpha': - dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") - itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") - else: - print "Unknown architecture, can't pick TLBs" - sys.exit(1) - else: - workload = VectorParam.Process("processes to run") - - max_insts_all_threads = Param.Counter(0, - "terminate when all threads have reached this inst count") - max_insts_any_thread = Param.Counter(0, - "terminate when any thread reaches this inst count") - max_loads_all_threads = Param.Counter(0, - "terminate when all threads have reached this load count") - max_loads_any_thread = Param.Counter(0, - "terminate when any thread reaches this load count") - progress_interval = Param.Tick(0, - "interval to print out the progress message") - - defer_registration = Param.Bool(False, - "defer registration with system (for sampling)") - - clock = Param.Clock('1t', "clock speed") - phase = Param.Latency('0ns', "clock phase") - - _mem_ports = [] - - def connectMemPorts(self, bus): - for p in self._mem_ports: - exec('self.%s = bus.port' % p) - - def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) == 2) - self.icache = ic - self.dcache = dc - self.icache_port = ic.cpu_side - self.dcache_port = dc.cpu_side - self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] - - def addTwoLevelCacheHierarchy(self, ic, dc, l2c): - self.addPrivateSplitL1Caches(ic, dc) - self.toL2Bus = Bus() - self.connectMemPorts(self.toL2Bus) - self.l2cache = l2c - self.l2cache.cpu_side = self.toL2Bus.port - self._mem_ports = ['l2cache.mem_side'] |