Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)

and PhysicalMemory.  *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
    and PhysicalMemory.  *No* support for caches or O3CPU.

--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be

1 files changed, 2 insertions, 1 deletions

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 0b887cceb..b6dc08e46 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -11,10 +11,11 @@ class BaseCPU(SimObject):
     mem = Param.MemObject("memory")
 
     system = Param.System(Parent.any, "system object")
+    cpu_id = Param.Int("CPU identifier")
+
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
-        cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")