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| author | Kevin Lim <ktlim@umich.edu> | 2006-11-10 12:44:15 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-10 12:44:15 -0500 |
| commit | b5e68fb54677f601bb00c23af52db8fd6571301f (patch) | |
| tree | dc3c17198ba4010d907ecd8cb7189aa7959948d4 /src/python/m5/objects/BaseCPU.py | |
| parent | 264f9ce374ff4689fec3c32d8289fe76b0b65078 (diff) | |
| parent | 9ef51f2dbaba88c10366d708f0ca872bb39064e4 (diff) | |
| download | gem5-b5e68fb54677f601bb00c23af52db8fd6571301f.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
Diffstat (limited to 'src/python/m5/objects/BaseCPU.py')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index b6dc08e46..b6e05627d 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -3,19 +3,27 @@ from m5.params import * from m5.proxy import * from m5 import build_env from AlphaTLB import AlphaDTB, AlphaITB +from SparcTLB import SparcDTB, SparcITB from Bus import Bus +import sys class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") cpu_id = Param.Int("CPU identifier") if build_env['FULL_SYSTEM']: - dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") - itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") + if build_env['TARGET_ISA'] == 'sparc': + dtb = Param.SparcDTB(SparcDTB(), "Data TLB") + itb = Param.SparcITB(SparcITB(), "Instruction TLB") + elif build_env['TARGET_ISA'] == 'alpha': + dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") + itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") + else: + print "Unknown architecture, can't pick TLBs" + sys.exit(1) else: workload = VectorParam.Process("processes to run") @@ -47,7 +55,6 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] -# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) |