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authorAli Saidi <saidi@eecs.umich.edu>2007-05-07 14:42:03 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-05-07 14:42:03 -0400
commit0dfc29a023ff407846ea4f200547e2b2d9de9c1a (patch)
treeea900fcfbb26455082766dfc99e39ab529f14e9c /src/python/m5/objects/Bus.py
parentb7292a1713afb95572dd0d379dcbb39d0bfd9191 (diff)
downloadgem5-0dfc29a023ff407846ea4f200547e2b2d9de9c1a.tar.xz
fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier --HG-- extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
Diffstat (limited to 'src/python/m5/objects/Bus.py')
-rw-r--r--src/python/m5/objects/Bus.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index 8226fe8d2..48dbbe307 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -11,6 +11,7 @@ class Bus(MemObject):
clock = Param.Clock("1GHz", "bus clock speed")
width = Param.Int(64, "bus width (bytes)")
responder_set = Param.Bool(False, "Did the user specify a default responder.")
+ block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
if build_env['FULL_SYSTEM']:
responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")